Unified Coverage Report :: Module :: flash_phy_rd_buf_dep

Module : flash_phy_rd_buf_dep

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.76	100.00	91.05			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.48			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Module : flash_phy_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T136
1	1	Covered	T1,T3,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T136
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Branch Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T5
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	798151312	6906157	0	0
BufferDepRsp_A	798151312	796342466	0	0
BufferIncrOverFlow_A	798151312	6906171	0	0
DepBufferRspOrder_A	798151313	16798009	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	798151312	6906157	0	0
T1	12106	201	0	0
T2	802482	0	0	0
T3	314276	43047	0	0
T4	258924	0	0	0
T5	1176926	712	0	0
T6	147208	25541	0	0
T10	2220	0	0	0
T11	6972	0	0	0
T13	2796	0	0	0
T14	138914	22176	0	0
T15	0	49257	0	0
T19	0	36161	0	0
T28	0	18987	0	0
T30	0	52	0	0
T50	0	42395	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	798151312	796342466	0	0
T1	12106	11998	0	0
T2	802482	802450	0	0
T3	314276	313996	0	0
T4	258924	208486	0	0
T5	1176926	1176746	0	0
T6	147208	146854	0	0
T10	2220	1846	0	0
T11	6972	5562	0	0
T13	2796	2678	0	0
T14	138914	138810	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	798151312	6906171	0	0
T1	12106	201	0	0
T2	802482	0	0	0
T3	314276	43047	0	0
T4	258924	0	0	0
T5	1176926	712	0	0
T6	147208	25541	0	0
T10	2220	0	0	0
T11	6972	0	0	0
T13	2796	0	0	0
T14	138914	22176	0	0
T15	0	49257	0	0
T19	0	36161	0	0
T28	0	18987	0	0
T30	0	52	0	0
T50	0	42395	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	798151313	16798009	0	0
T1	12106	233	0	0
T2	802482	263744	0	0
T3	314276	43103	0	0
T4	258924	0	0	0
T5	1176926	744	0	0
T6	147208	25605	0	0
T10	2220	67	0	0
T11	6972	162	0	0
T13	2796	32	0	0
T14	138914	22208	0	0
T15	0	49289	0	0
T19	0	16715	0	0
T28	0	8581	0	0
T30	0	40	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T16,T136
1	1	Covered	T1,T3,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T136
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T5
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	399075656	3551217	0	0
BufferDepRsp_A	399075656	398171233	0	0
BufferIncrOverFlow_A	399075656	3551224	0	0
DepBufferRspOrder_A	399075657	8870573	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	3551217	0	0
T1	6053	128	0	0
T2	401241	0	0	0
T3	157138	21361	0	0
T4	129462	0	0	0
T5	588463	336	0	0
T6	73604	17216	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	12979	0	0
T15	0	25917	0	0
T19	0	19446	0	0
T28	0	10406	0	0
T30	0	12	0	0
T50	0	22785	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	3551224	0	0
T1	6053	128	0	0
T2	401241	0	0	0
T3	157138	21361	0	0
T4	129462	0	0	0
T5	588463	336	0	0
T6	73604	17216	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	12979	0	0
T15	0	25917	0	0
T19	0	19446	0	0
T28	0	10406	0	0
T30	0	12	0	0
T50	0	22785	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075657	8870573	0	0
T1	6053	160	0	0
T2	401241	132672	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	368	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	25949	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T56,T107
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T138,T75
1	1	Covered	T1,T3,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T138,T75
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T5
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	399075656	3354940	0	0
BufferDepRsp_A	399075656	398171233	0	0
BufferIncrOverFlow_A	399075656	3354947	0	0
DepBufferRspOrder_A	399075656	7927436	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	3354940	0	0
T1	6053	73	0	0
T2	401241	0	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	376	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	23340	0	0
T19	0	16715	0	0
T28	0	8581	0	0
T30	0	40	0	0
T50	0	19610	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	3354947	0	0
T1	6053	73	0	0
T2	401241	0	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	376	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	23340	0	0
T19	0	16715	0	0
T28	0	8581	0	0
T30	0	40	0	0
T50	0	19610	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	7927436	0	0
T1	6053	73	0	0
T2	401241	131072	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	376	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	23340	0	0
T19	0	16715	0	0
T28	0	8581	0	0
T30	0	40	0	0