d09e282b26| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 4.602m | 2.735ms | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 27.000s | 15.122us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 46.250s | 162.392us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 18.660s | 483.163us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.485m | 20.450ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.029m | 6.443ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 20.060s | 50.711us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 18.660s | 483.163us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.029m | 6.443ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.690s | 16.678us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.840s | 26.379us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 27.650s | 20.982us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.881m | 115.283us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 38.098m | 669.195ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 19.161m | 240.219ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.790s | 15.582us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 44.282m | 273.210ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 9.540m | 4.086ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 3.501m | 2.382ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.236h | 101.742ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.233m | 3.168ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 31.890s | 51.444us | 30 | 40 | 75.00 |
| flash_ctrl_rw_evict_all_en | 32.260s | 71.018us | 29 | 40 | 72.50 | ||
| flash_ctrl_re_evict | 36.310s | 68.496us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 10.670m | 2.817ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 10.670m | 2.817ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 14.106m | 53.091ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 30.690s | 2.220ms | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 22.200m | 1.574ms | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 46.077m | 7.255ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 16.356m | 1.492ms | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 44.412m | 3.763ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.050s | 26.412us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 3.723m | 1.704ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 22.820s | 42.427us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.770s | 27.326us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 9.141m | 224.391us | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.554m | 3.470ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.254m | 149.474us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 38.098m | 669.195ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.026m | 25.649ms | 39 | 40 | 97.50 |
| flash_ctrl_intr_wr | 1.351m | 9.492ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 6.971m | 151.591ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 4.540m | 54.673ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.522m | 4.578ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.324m | 7.236ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 23.090s | 126.517us | 5 | 5 | 100.00 |
| flash_ctrl_ro_derr | 2.887m | 7.187ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 4.667m | 8.983ms | 10 | 10 | 100.00 | ||
| flash_ctrl_derr_detect | 3.545m | 2.134ms | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 12.087m | 4.887ms | 5 | 5 | 100.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 23.320s | 111.771us | 5 | 5 | 100.00 |
| flash_ctrl_ro_serr | 2.625m | 8.094ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 4.957m | 4.708ms | 10 | 10 | 100.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.404m | 1.597ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.679m | 3.927ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.109m | 3.015ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 15.310s | 106.370us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 14.440s | 83.034us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.407m | 4.095ms | 20 | 20 | 100.00 | ||
| flash_ctrl_rw | 10.954m | 30.446ms | 19 | 20 | 95.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 39.550s | 1.228ms | 3 | 5 | 60.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 17.097m | 159.316ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 5.618m | 10.012ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.730s | 140.951us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.010s | 18.454us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20.490s | 279.424us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20.490s | 279.424us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 46.250s | 162.392us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.660s | 483.163us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.029m | 6.443ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.460s | 1.084ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 46.250s | 162.392us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 18.660s | 483.163us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.029m | 6.443ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.460s | 1.084ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 988 | 1013 | 97.53 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.660s | 86.748us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.660s | 86.748us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.660s | 86.748us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.660s | 86.748us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 16.410s | 11.413us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.300m | 1.717ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.300m | 1.717ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.300m | 1.717ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.400s | 111.465us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.070s | 81.629us | 2 | 3 | 66.67 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 4.602m | 2.735ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.254m | 149.474us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 22.820s | 42.427us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.717m | 39.164ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.770s | 27.326us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.430s | 88.647us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 18.660s | 483.163us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.660s | 86.748us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 18.660s | 483.163us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.660s | 86.748us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 18.660s | 483.163us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.660s | 86.748us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 22.820s | 42.427us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.400s | 111.465us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.890s | 40.249us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_addr_infection | flash_ctrl_host_addr_infection | 31.300s | 27.836us | 3 | 3 | 100.00 |
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 22.820s | 42.427us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 30.690s | 2.220ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 10.954m | 30.446ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 4.957m | 4.708ms | 10 | 10 | 100.00 |
| flash_ctrl_rw_derr | 4.667m | 8.983ms | 10 | 10 | 100.00 | ||
| flash_ctrl_integrity | 12.087m | 4.887ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 38.098m | 669.195ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 18.330s | 948.127us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.180s | 24.008us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 19.090s | 79.436us | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.389h | 1.925ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 146 | 147 | 99.32 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 48.080s | 100.122us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1255 | 1281 | 97.97 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 50 | 90.91 |
| V2S | 13 | 13 | 12 | 92.31 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.22 | 95.67 | 93.81 | 98.31 | 92.52 | 98.12 | 96.89 | 98.21 |
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:
2.flash_ctrl_rw_evict.72752740282965498495181539802916453488843244502899405274193699457456405431781
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 12176.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 12176.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.flash_ctrl_rw_evict.98901420831209528379158322801457955825941235712667681798729572099781027015309
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 24519.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 24519.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
9.flash_ctrl_rw_evict_all_en.36495713732966876579372973819716761131779271836852976549745244460145990332945
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 22189.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 22189.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:
Test flash_ctrl_fs_sup has 2 failures.
2.flash_ctrl_fs_sup.96995851608568892046983305338229774111193301433043088254939750039949643941352
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest/run.log
UVM_ERROR @ 216784.5 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 216784.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.flash_ctrl_fs_sup.23990733697221677243836444528023039843800969554689128021844947515311434350325
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest/run.log
UVM_ERROR @ 850442.9 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 850442.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw has 1 failures.
13.flash_ctrl_rw.107794248390735807082539186150040911589997490014720845043931643838974741443512
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest/run.log
UVM_ERROR @ 19627.2 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 19627.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *d5b852_*:ffffffff_ffffffff mismatch!! has 1 failures:
0.flash_ctrl_intr_rd.87171283697612130150665039388783019250056192314614452475449811414003004241301
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 13529703.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 6: obs:exp 02d5b852_18449597:ffffffff_ffffffff mismatch!!
UVM_INFO @ 13529703.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank1] *: obs:exp ff_*_6378dda2_3fad40c6:ce_*_6378dda2_3fad40c* mismatch!! has 1 failures:
1.flash_ctrl_wr_intg.12848459633022951145627547974182317109479341177407052948257458123850628177880
Line 304, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest/run.log
UVM_ERROR @ 117274.5 ns: (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank1] 0: obs:exp ff_3_6378dda2_3fad40c6:ce_3_6378dda2_3fad40c6 mismatch!!
UVM_INFO @ 117274.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152477) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.flash_ctrl_rw_evict.38951278735081173517289915543835349398572541936697761950869071631920367292950
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 10723.9 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152477) { a_addr: 'h237d0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hec a_opcode: 'h4 a_user: 'h24d2a d_param: 'h0 d_source: 'hec d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 10723.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152078) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.flash_ctrl_rw_evict.113444061972891707013270971413372737486549579045569224751486558015921595301672
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 30224.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152078) { a_addr: 'h64dd8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6c a_opcode: 'h4 a_user: 'h242aa d_param: 'h0 d_source: 'h6c d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 30224.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153210) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.flash_ctrl_rw_evict_all_en.102913777829734724999107318810482536965583506180650221895794309467780407438146
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 14698.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153210) { a_addr: 'ha988 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4b a_opcode: 'h4 a_user: 'h24baa d_param: 'h0 d_source: 'h4b d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 14698.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@159005) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.flash_ctrl_rw_evict.11445563311703400931400838779798368767662562580883445173828970610497440748985
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 12980.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@159005) { a_addr: 'he9fd8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h82 a_opcode: 'h4 a_user: 'h26eaa d_param: 'h0 d_source: 'h82 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 12980.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155755) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.flash_ctrl_rw_evict_all_en.114756458623868287339755733614374217070543439379733965897864517430534673517530
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 49780.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155755) { a_addr: 'hc68a0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h264aa d_param: 'h0 d_source: 'h21 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 49780.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153777) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.flash_ctrl_rw_evict_all_en.9678218852954005453182316112804303372525627562793234403888131109908751834185
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 18731.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153777) { a_addr: 'h12c80 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h44 a_opcode: 'h4 a_user: 'h27b2a d_param: 'h0 d_source: 'h44 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 18731.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152778) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.flash_ctrl_rw_evict_all_en.18736917112378123348509662299063732410205892479004989486099628158796516114566
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 22102.9 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152778) { a_addr: 'hea7d8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h255aa d_param: 'h0 d_source: 'h3c d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 22102.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153419) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.flash_ctrl_rw_evict.8967840073118472702993351904085144264940138720704508753389352925607942439038
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 9281.4 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153419) { a_addr: 'h7c408 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h55 a_opcode: 'h4 a_user: 'h26a2a d_param: 'h0 d_source: 'h55 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 9281.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152419) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
15.flash_ctrl_rw_evict.82650145788964330588839640313435234267870717874959627341828972969530300926730
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 8183.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152419) { a_addr: 'h30dc8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h2642a d_param: 'h0 d_source: 'h34 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 8183.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151632) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.flash_ctrl_rw_evict_all_en.73489601505797035386118946425995499377072223814586446869435767886373674891473
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 49756.8 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151632) { a_addr: 'hee280 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h27c2a d_param: 'h0 d_source: 'h2e d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 49756.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157037) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
23.flash_ctrl_rw_evict.20686812390349667546015411310949813123215217355736747768439012961039377931256
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 45093.2 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157037) { a_addr: 'hd3f98 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hca a_opcode: 'h4 a_user: 'h2522a d_param: 'h0 d_source: 'hca d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 45093.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153235) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
26.flash_ctrl_rw_evict.60542398216635738092612749635403112679828004716211095205222805603266863024671
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 9077.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153235) { a_addr: 'h442f8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h2572a d_param: 'h0 d_source: 'h3 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 9077.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154411) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
29.flash_ctrl_rw_evict_all_en.40545412551241200057590003071449785969422976057395103021058977610188746720736
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 8162.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154411) { a_addr: 'h9e3c0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7c a_opcode: 'h4 a_user: 'h245aa d_param: 'h0 d_source: 'h7c d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 8162.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156098) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
31.flash_ctrl_rw_evict_all_en.53595745172830153514853042764181084581740482842517745287864024025883297869650
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 18368.2 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156098) { a_addr: 'h75840 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h25 a_opcode: 'h4 a_user: 'h2722a d_param: 'h0 d_source: 'h25 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 18368.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155239) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
37.flash_ctrl_rw_evict_all_en.37598079156977049112784885367538126169727093800718557605627304844372746794937
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 20919.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155239) { a_addr: 'h28810 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h2682a d_param: 'h0 d_source: 'h5 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 20919.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154751) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
38.flash_ctrl_rw_evict_all_en.13172311919534163129599542225689063156327826833005411792642886971950314885561
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 30933.0 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154751) { a_addr: 'hd2088 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'ha d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 30933.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154227) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
39.flash_ctrl_rw_evict_all_en.36607375646129902982887874745590285773522771011298056584704595902490317062748
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 19435.2 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154227) { a_addr: 'h69468 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd5 a_opcode: 'h4 a_user: 'h25b2a d_param: 'h0 d_source: 'hd5 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 19435.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---