FLASH_CTRL Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.585m	1.615ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.290s	27.936us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.200s	26.393us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.410s	139.676us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.332m	10.938ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.175m	12.128ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.410s	157.788us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.410s	139.676us	20	20	100.00
		flash_ctrl_csr_aliasing	1.175m	12.128ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.370s	76.272us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.350s	75.255us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.910s	77.049us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.940m	122.573us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.996m	277.737ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.931m	760.416ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.010s	26.051us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	58.401m	293.704ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.227m	2.132ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.253m	11.013ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.273h	244.545ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.053m	1.414ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.650s	138.700us	30	40	75.00
		flash_ctrl_rw_evict_all_en	32.550s	140.443us	34	40	85.00
		flash_ctrl_re_evict	36.530s	227.299us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.635m	2.109ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.635m	2.109ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.845m	48.004ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	32.350s	2.328ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.346m	222.614us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	40.103m	4.989ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.295m	1.004ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	54.481m	5.185ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.640s	111.983us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.690m	1.346ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.860s	17.483us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.630s	56.133us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	32.150m	3.451ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.201m	3.299ms	50	50	100.00
		flash_ctrl_otp_reset	2.279m	154.544us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.996m	277.737ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.439m	6.741ms	39	40	97.50
		flash_ctrl_intr_wr	1.520m	23.766ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.309m	49.551ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.268m	118.882ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.532m	4.421ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.240m	3.225ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.770s	32.243us	5	5	100.00
		flash_ctrl_ro_derr	2.528m	2.471ms	10	10	100.00
		flash_ctrl_rw_derr	4.589m	7.755ms	10	10	100.00
		flash_ctrl_derr_detect	3.478m	896.114us	5	5	100.00
		flash_ctrl_integrity	10.082m	4.657ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.590s	86.096us	5	5	100.00
		flash_ctrl_ro_serr	2.347m	1.273ms	10	10	100.00
		flash_ctrl_rw_serr	4.150m	7.539ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.134m	683.783us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.767m	7.271ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.197m	11.827ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.130s	42.196us	1	1	100.00
		flash_ctrl_read_word_sweep	13.990s	24.206us	1	1	100.00
		flash_ctrl_ro	2.055m	702.536us	19	20	95.00
		flash_ctrl_rw	13.752m	42.211ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	41.650s	630.230us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	24.389m	88.279ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.183m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.460s	266.058us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.250s	95.211us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.300s	276.583us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.300s	276.583us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.200s	26.393us	5	5	100.00
		flash_ctrl_csr_rw	17.410s	139.676us	20	20	100.00
		flash_ctrl_csr_aliasing	1.175m	12.128ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.920s	317.697us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.200s	26.393us	5	5	100.00
		flash_ctrl_csr_rw	17.410s	139.676us	20	20	100.00
		flash_ctrl_csr_aliasing	1.175m	12.128ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.920s	317.697us	20	20	100.00
V2		TOTAL			994	1013	98.12
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.320s	12.674us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.320s	12.674us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.320s	12.674us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.320s	12.674us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.550s	12.474us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.095m	726.763us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.095m	726.763us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.095m	726.763us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.720s	207.563us	3	3	100.00
		flash_ctrl_wr_intg	15.210s	45.627us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.585m	1.615ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.279m	154.544us	80	80	100.00
		flash_ctrl_disable	22.860s	17.483us	50	50	100.00
		flash_ctrl_sec_info_access	1.641m	22.714ms	50	50	100.00
		flash_ctrl_connect	16.630s	56.133us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.970s	37.089us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.410s	139.676us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.320s	12.674us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.410s	139.676us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.320s	12.674us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.410s	139.676us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.320s	12.674us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.860s	17.483us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.720s	207.563us	3	3	100.00
		flash_ctrl_access_after_disable	13.800s	22.172us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.220s	64.556us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.860s	17.483us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	32.350s	2.328ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	13.752m	42.211ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.150m	7.539ms	10	10	100.00
		flash_ctrl_rw_derr	4.589m	7.755ms	10	10	100.00
		flash_ctrl_integrity	10.082m	4.657ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.996m	277.737ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.120s	915.549us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.260s	49.052us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.440s	18.112us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.382h	1.071ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	46.450s	288.922us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1262	1281	98.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.27	95.74	93.91	98.31	92.52	98.34	96.89	98.21

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151575) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

2.flash_ctrl_rw_evict.114908138702829416678967502289636661688033562105599622829854632368233202873560
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 14049.8 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151575) { a_addr: 'h1fe90  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hbc  a_opcode: 'h4  a_user: 'h265aa  d_param: 'h0  d_source: 'hbc  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 14049.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.11794469250752782049346300210169068377306964500207251757930241828184708383198
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 12751654.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000600
  UVM_INFO @ 12751654.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155215) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

4.flash_ctrl_rw_evict_all_en.88490584079187345245913297670322248089085775315247921100723768557241056697398
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 43659.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155215) { a_addr: 'hb0a28  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h26daa  d_param: 'h0  d_source: 'h9  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 43659.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153830) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

6.flash_ctrl_rw_evict.86723762891566594325407479898082852770489683380126205396706951228077274108564
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 9192.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153830) { a_addr: 'h5eb38  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h24e2a  d_param: 'h0  d_source: 'hd  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 9192.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 7.flash_ctrl_ro.12004367281327397212997340862216922983832719484490648311034818318156955411758
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 55185.3 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 55185.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153681) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

7.flash_ctrl_rw_evict.55170944307131084722212637958990894838208086965537233827628379942010940676612
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 9002.0 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153681) { a_addr: 'hfab00  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hce  a_opcode: 'h4  a_user: 'h264aa  d_param: 'h0  d_source: 'hce  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 9002.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153210) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

8.flash_ctrl_rw_evict_all_en.82792172811889728252386809143855735856368137658247102883984241850087903267931
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 64778.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153210) { a_addr: 'hb3268  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h79  a_opcode: 'h4  a_user: 'h27e2a  d_param: 'h0  d_source: 'h79  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 64778.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154778) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

10.flash_ctrl_rw_evict.73093306956050305394086078761326194303037796699742907713364416054909896087825
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 41428.9 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154778) { a_addr: 'h61200  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6e  a_opcode: 'h4  a_user: 'h27eaa  d_param: 'h0  d_source: 'h6e  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 41428.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154051) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

18.flash_ctrl_rw_evict.830319299090801861494266044723108031540519046602174836157138661174566301103
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 9259.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154051) { a_addr: 'hf05b0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h25f2a  d_param: 'h0  d_source: 'h2a  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 9259.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154186) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

18.flash_ctrl_rw_evict_all_en.72347624221586776878869381327549985683871640336753626307785917687498360174810
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 19496.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154186) { a_addr: 'hdd6b0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h44  a_opcode: 'h4  a_user: 'h2532a  d_param: 'h0  d_source: 'h44  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 19496.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153599) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

22.flash_ctrl_rw_evict.21620551717279261906021559325886644833671081212122035895627760739386737899888
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 44428.4 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153599) { a_addr: 'h23038  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h54  a_opcode: 'h4  a_user: 'h2462a  d_param: 'h0  d_source: 'h54  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 44428.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@159656) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

26.flash_ctrl_rw_evict.61327101406052955183986799527220011767862213247438118848817591373207132951523
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 27432.9 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@159656) { a_addr: 'h2fd20  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h27d2a  d_param: 'h0  d_source: 'h38  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 27432.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156315) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

27.flash_ctrl_rw_evict.47278659931209546103437585007966200359913478389469071251714676968136441404766
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 11460.2 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156315) { a_addr: 'hdefb8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h63  a_opcode: 'h4  a_user: 'h27baa  d_param: 'h0  d_source: 'h63  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 11460.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153027) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

27.flash_ctrl_rw_evict_all_en.13383334961561571396551634097048605689859125756154575320333122532514770437059
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 10688.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153027) { a_addr: 'h5f028  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb3  a_opcode: 'h4  a_user: 'h248aa  d_param: 'h0  d_source: 'hb3  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 10688.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *_c6385cc6:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 28.flash_ctrl_intr_rd.110128524069985081838614549506169247176709149946282335241332047115732756941501
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 10156894.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    93840423_c6385cc6:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 10156894.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153426) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

28.flash_ctrl_rw_evict_all_en.109335163686731967424508813187327650671683218356332809172858064381431808129821
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 8920.2 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153426) { a_addr: 'haaa60  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h73  a_opcode: 'h4  a_user: 'h274aa  d_param: 'h0  d_source: 'h73  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 8920.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153268) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

30.flash_ctrl_rw_evict_all_en.10626177269094746962901687842855708201327789622148995375580918015188481755413
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 8910.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153268) { a_addr: 'h15688  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h75  a_opcode: 'h4  a_user: 'h27aaa  d_param: 'h0  d_source: 'h75  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 8910.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 33.flash_ctrl_rw_evict.107524099210251847479660365291271117923749018512448191359547295828107674496620
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 68990.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 68990.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155968) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

38.flash_ctrl_rw_evict.112878035908327411561675451700889916550873830809547836251911355928156209687778
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 42737.3 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155968) { a_addr: 'h43a40  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h99  a_opcode: 'h4  a_user: 'h2512a  d_param: 'h0  d_source: 'h99  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 42737.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---