Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync	100.00	100.00					100.00
tb.dut.u_lc_seed_hw_rd_en_sync	100.00	100.00					100.00
tb.dut.u_flash_hw_if.u_sync_rma_req	100.00	100.00					100.00
tb.dut.u_prog_tl_gate.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_lc_escalation_en_sync	100.00	100.00					100.00
tb.dut.u_tl_gate.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.75	100.00	92.71		92.11	98.94	100.00	u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.37	100.00	88.89		57.14	95.83	50.00	u_prog_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_escalation_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.60	100.00	100.00		57.14	95.83	50.00	u_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_lc_seed_hw_rd_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prog_tl_gate.u_err_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	5	5

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10430	10430	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.OutputDelay_A	2147483647	2147483647	0	21642
gen_no_flops.OutputDelay_A	781053444	779329952	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10430	10430	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T10	10	10	0	0
T17	10	10	0	0
T18	10	10	0	0
T19	10	10	0	0
T20	10	10	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	39420	38790	0	0
T2	16730	15200	0	0
T3	2570180	2458090	0	0
T4	50110	47190	0	0
T5	1505700	1504740	0	0
T10	3948890	3948730	0	0
T17	14040	12670	0	0
T18	4100	3120	0	0
T19	17410	16480	0	0
T20	3720	3200	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	21642
T1	31536	31008	0	24
T2	13384	12112	0	24
T3	2056144	1962776	0	24
T4	40088	37656	0	24
T5	1204560	1203768	0	24
T10	3159112	3158976	0	24
T11	0	0	0	21
T12	0	0	0	3
T17	11232	10088	0	24
T18	3280	2496	0	0
T19	13928	13160	0	24
T20	2976	2560	0	0
T55	0	0	0	24

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	781053444	779329952	0	0
T1	7884	7758	0	0
T2	3346	3040	0	0
T3	514036	491618	0	0
T4	10022	9438	0	0
T5	301140	300948	0	0
T10	789778	789746	0	0
T17	2808	2534	0	0
T18	820	624	0	0
T19	3482	3296	0	0
T20	744	640	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526861	389665115	0	0
gen_flops.OutputDelay_A	390526861	389631074	0	2724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389665115	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389631074	0	2724
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T11	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526861	389665115	0	0
gen_flops.OutputDelay_A	390526861	389631074	0	2724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389665115	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389631074	0	2724
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T11	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526861	389665115	0	0
gen_flops.OutputDelay_A	390526861	389631074	0	2724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389665115	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389631074	0	2724
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T11	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526861	389665115	0	0
gen_flops.OutputDelay_A	390526861	389631074	0	2724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389665115	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389631074	0	2724
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T11	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526861	389665115	0	0
gen_flops.OutputDelay_A	390526861	389631074	0	2724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389665115	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389631074	0	2724
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T11	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526861	389665115	0	0
gen_flops.OutputDelay_A	390526861	389631074	0	2724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389665115	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526861	389631074	0	2724
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T11	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526722	389664976	0	0
gen_no_flops.OutputDelay_A	390526722	389664976	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526722	389664976	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526722	389664976	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_lc_escalation_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390502606	389640860	0	0
gen_flops.OutputDelay_A	390502606	389606969	0	2574

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390502606	389640860	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390502606	389606969	0	2574
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T12	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3

Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526722	389664976	0	0
gen_no_flops.OutputDelay_A	390526722	389664976	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526722	389664976	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526722	389664976	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	5	5

---

Assert Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1043	1043	0	0
OutputsKnown_A	390526722	389664976	0	0
gen_flops.OutputDelay_A	390526722	389630950	0	2724

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526722	389664976	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	410	312	0	0
T19	1741	1648	0	0
T20	372	320	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390526722	389630950	0	2724
T1	3942	3876	0	3
T2	1673	1514	0	3
T3	257018	245347	0	3
T4	5011	4707	0	3
T5	150570	150471	0	3
T10	394889	394872	0	3
T11	0	0	0	3
T17	1404	1261	0	3
T18	410	312	0	0
T19	1741	1645	0	3
T20	372	320	0	0
T55	0	0	0	3