Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 97.12 94.40 98.44 100.00 84.29

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.85 97.12 94.40 98.44 100.00 84.29



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 97.12 94.40 98.44 100.00 84.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 95.74 93.99 98.31 92.52 98.31 96.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
flash_ctrl_core_csr_assert 100.00 100.00
gen_alert_senders[0].u_alert_sender 100.00 100.00
gen_alert_senders[1].u_alert_sender 100.00 100.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 100.00 100.00
gen_alert_senders[4].u_alert_sender 77.78 77.78
tlul_assert_device 99.65 100.00 100.00 98.95
u_ctrl_arb 100.00 100.00 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_eflash 97.45 98.05 93.20 99.49 97.62 99.40 96.96
u_exec_en_buf 100.00 100.00
u_flash_ctrl_erase 100.00 100.00 100.00 100.00
u_flash_ctrl_prog 97.88 100.00 97.06 100.00 94.44
u_flash_ctrl_rd 94.44 83.02 93.94 100.00 100.00 95.24
u_flash_hw_if 96.34 99.27 93.52 95.83 92.11 97.30 100.00
u_flash_mp 99.69 100.00 98.77 100.00 100.00
u_intr_corr_err 93.75 100.00 75.00 100.00 100.00
u_intr_op_done 93.75 100.00 75.00 100.00 100.00
u_intr_prog_empty 86.94 90.00 77.78 80.00 100.00
u_intr_prog_lvl 86.94 90.00 77.78 80.00 100.00
u_intr_rd_full 86.94 90.00 77.78 80.00 100.00
u_intr_rd_lvl 86.94 90.00 77.78 80.00 100.00
u_lc_escalation_en_sync 100.00 100.00 100.00 100.00
u_lc_seed_hw_rd_en_sync 100.00 100.00 100.00 100.00
u_lfsr 100.00 100.00
u_prog_fifo 97.73 100.00 90.91 100.00 100.00
u_prog_tl_gate 86.16 100.00 89.29 57.14 96.88 87.50
u_reg_core 99.30 99.00 98.60 100.00 98.92 100.00
u_reg_idle 100.00 100.00 100.00
u_region_cfg 87.91 63.73 100.00 100.00
u_sw_rd_fifo 93.67 95.12 88.64 90.91 100.00
u_tl_adapter_eflash 93.96 92.89 82.72 97.66 96.55 100.00
u_tl_gate 85.54 100.00 89.29 57.14 93.75 87.50
u_to_prog_fifo 79.77 89.66 65.61 82.56 81.25
u_to_rd_fifo 86.03 87.86 75.35 80.00 86.96 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
TOTAL13913597.12
CONT_ASSIGN40511100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN50111100.00
CONT_ASSIGN57111100.00
CONT_ASSIGN57511100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN62111100.00
CONT_ASSIGN62611100.00
ALWAYS63055100.00
CONT_ASSIGN67311100.00
CONT_ASSIGN67411100.00
CONT_ASSIGN67511100.00
CONT_ASSIGN69511100.00
CONT_ASSIGN69911100.00
CONT_ASSIGN73011100.00
ALWAYS75177100.00
CONT_ASSIGN78411100.00
CONT_ASSIGN78511100.00
CONT_ASSIGN85611100.00
CONT_ASSIGN85811100.00
CONT_ASSIGN85911100.00
CONT_ASSIGN86011100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86211100.00
CONT_ASSIGN86311100.00
CONT_ASSIGN86411100.00
CONT_ASSIGN86511100.00
CONT_ASSIGN86611100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN86911100.00
CONT_ASSIGN87211100.00
CONT_ASSIGN87511100.00
CONT_ASSIGN87811100.00
CONT_ASSIGN880100.00
CONT_ASSIGN882100.00
CONT_ASSIGN88611100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN88911100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89511100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN89911100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN904100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90711100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN93711100.00
CONT_ASSIGN94211100.00
CONT_ASSIGN94511100.00
CONT_ASSIGN94811100.00
CONT_ASSIGN95011100.00
CONT_ASSIGN95811100.00
CONT_ASSIGN101111100.00
CONT_ASSIGN101511100.00
CONT_ASSIGN102711100.00
CONT_ASSIGN102811100.00
CONT_ASSIGN104211100.00
CONT_ASSIGN105611100.00
CONT_ASSIGN105711100.00
CONT_ASSIGN107511100.00
CONT_ASSIGN107611100.00
CONT_ASSIGN107711100.00
CONT_ASSIGN107811100.00
CONT_ASSIGN107911100.00
CONT_ASSIGN108011100.00
CONT_ASSIGN108111100.00
CONT_ASSIGN1082100.00
CONT_ASSIGN108311100.00
CONT_ASSIGN108411100.00
CONT_ASSIGN110511100.00
CONT_ASSIGN110611100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN110811100.00
CONT_ASSIGN110911100.00
CONT_ASSIGN111011100.00
CONT_ASSIGN111111100.00
CONT_ASSIGN111211100.00
CONT_ASSIGN111311100.00
CONT_ASSIGN111411100.00
CONT_ASSIGN111511100.00
CONT_ASSIGN111611100.00
CONT_ASSIGN112811100.00
CONT_ASSIGN113011100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
CONT_ASSIGN113511100.00
CONT_ASSIGN113611100.00
CONT_ASSIGN113711100.00
CONT_ASSIGN114111100.00
CONT_ASSIGN114111100.00
CONT_ASSIGN114211100.00
CONT_ASSIGN114211100.00
CONT_ASSIGN114611100.00
CONT_ASSIGN114611100.00
CONT_ASSIGN114711100.00
CONT_ASSIGN114711100.00
CONT_ASSIGN115211100.00
CONT_ASSIGN115411100.00
CONT_ASSIGN115511100.00
CONT_ASSIGN115711100.00
CONT_ASSIGN115911100.00
CONT_ASSIGN116011100.00
CONT_ASSIGN126311100.00
CONT_ASSIGN126411100.00
CONT_ASSIGN128011100.00
CONT_ASSIGN140011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
405 1 1
406 1 1
407 1 1
408 1 1
409 1 1
410 1 1
411 1 1
412 1 1
413 1 1
414 1 1
415 1 1
416 1 1
501 1 1
571 1 1
575 1 1
577 1 1
621 1 1
626 1 1
630 1 1
631 1 1
632 1 1
634 1 1
635 1 1
673 1 1
674 1 1
675 1 1
695 1 1
699 1 1
730 1 1
751 1 1
753 1 1
754 1 1
757 1 1
758 1 1
761 1 1
762 1 1
784 1 1
785 1 1
856 1 1
858 1 1
859 1 1
860 1 1
861 1 1
862 1 1
863 1 1
864 1 1
865 1 1
866 1 1
867 1 1
869 1 1
872 1 1
875 1 1
878 1 1
880 0 1
882 0 1
886 1 1
887 1 1
888 1 1
889 1 1
890 1 1
891 1 1
892 1 1
893 1 1
894 1 1
895 1 1
896 1 1
897 1 1
898 1 1
899 1 1
900 1 1
901 1 1
903 1 1
904 0 1
905 1 1
906 1 1
907 1 1
913 1 1
937 1 1
942 1 1
945 1 1
948 1 1
950 1 1
958 1 1
1011 1 1
1015 1 1
1027 1 1
1028 1 1
1042 1 1
1056 1 1
1057 1 1
1075 1 1
1076 1 1
1077 1 1
1078 1 1
1079 1 1
1080 1 1
1081 1 1
1082 0 1
1083 1 1
1084 1 1
1105 1 1
1106 1 1
1107 1 1
1108 1 1
1109 1 1
1110 1 1
1111 1 1
1112 1 1
1113 1 1
1114 1 1
1115 1 1
1116 1 1
1128 1 1
1130 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1
1135 1 1
1136 1 1
1137 1 1
1141 2 2
1142 2 2
1146 2 2
1147 2 2
1152 1 1
1154 1 1
1155 1 1
1157 1 1
1159 1 1
1160 1 1
1263 1 1
1264 1 1
1280 1 1
1400 1 1


Cond Coverage for Module : flash_ctrl
TotalCoveredPercent
Conditions12511894.40
Logical12511894.40
Non-Logical00
Event00

 LINE       331
 EXPRESSION (sw_wvalid & prog_op_valid)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T80,T81
11CoveredT1,T2,T3

 LINE       413
 EXPRESSION (op_type == FlashOpRead)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       414
 EXPRESSION (op_type == FlashOpProgram)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       415
 EXPRESSION (op_type == FlashOpErase)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T10

 LINE       416
 EXPRESSION (if_sel == SwSel)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       423
 EXPRESSION (((~sw_sel)) & rd_ctrl_wen)
             -----1-----   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       501
 EXPRESSION (op_start & prog_op)
             ----1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       557
 EXPRESSION (reg2hw.fifo_rst.q | fifo_clr | sw_ctrl_done)
             --------1--------   ----2---   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100Not Covered

 LINE       575
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgNormal] & reg2hw.prog_type_en.normal.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT82,T83,T84
11CoveredT1,T2,T3

 LINE       577
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgRepair] & reg2hw.prog_type_en.repair.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT82,T83,T85
11CoveredT1,T2,T3

 LINE       621
 EXPRESSION (reg2hw.control.start.q & (reg2hw.control.op.q == FlashOpRead))
             -----------1----------   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       621
 SUB-EXPRESSION (reg2hw.control.op.q == FlashOpRead)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       634
 EXPRESSION (adapter_req & sw_rfifo_rvalid)
             -----1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T22
11CoveredT1,T2,T3

 LINE       647
 EXPRESSION (sw_rfifo_rvalid | rd_no_op_d)
             -------1-------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT42,T7,T43
10CoveredT1,T2,T3

 LINE       647
 EXPRESSION (adapter_rvalid | rd_no_op_q)
             -------1------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT42,T7,T43
10CoveredT1,T2,T3

 LINE       673
 EXPRESSION (sw_sel & rd_ctrl_wen)
             ---1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       699
 EXPRESSION (op_start & rd_op)
             ----1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       700
 EXPRESSION (sw_sel ? sw_rfifo_wready : lcmgr_rready)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       730
 EXPRESSION (op_start & erase_op)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT1,T3,T10
10CoveredT1,T2,T3
11CoveredT1,T3,T10

 LINE       794
 EXPRESSION (rd_flash_ovfl | prog_flash_ovfl)
             ------1------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT86,T87

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashErasePage))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T88,T68
11CoveredT1,T3,T10

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashErasePage)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashEraseBank))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T17
10CoveredT1,T3,T10
11CoveredT10,T88,T68

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashEraseBank)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T17

 LINE       867
 EXPRESSION (flash_phy_busy | ctrl_init_busy)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       869
 EXPRESSION (ctrl_initialized & ((~flash_phy_busy)))
             --------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT89,T81,T90
11CoveredT1,T2,T3

 LINE       875
 EXPRESSION (sw_sel ? ((!op_start)) : 1'b1)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       913
 SUB-EXPRESSION (flash_phy_req.req & (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase))
                 --------1--------   -----------------------------------2----------------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       913
 SUB-EXPRESSION (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase)
                 ---------1--------   -----------2----------   -----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT10,T68,T69
010CoveredT1,T3,T10
100CoveredT1,T2,T3

 LINE       937
 EXPRESSION ((sw_ctrl_done & ((|sw_ctrl_err))) | flash_phy_rsp.macro_err | update_err)
             ----------------1----------------   -----------2-----------   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT2,T5,T11

 LINE       937
 SUB-EXPRESSION (sw_ctrl_done & ((|sw_ctrl_err)))
                 ------1-----   --------2-------
-1--2-StatusTests
01CoveredT2,T5,T22
10CoveredT1,T2,T3
11CoveredT2,T5,T11

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT91,T92,T93
10CoveredT1,T2,T3
11CoveredT91,T92,T93

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT91,T92,T93
10CoveredT1,T2,T3
11CoveredT91,T92,T93

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT91,T92,T93
10CoveredT1,T2,T3
11CoveredT91,T92,T93

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe)
                 ----------------1----------------   -----------------2----------------
-1--2-StatusTests
01CoveredT91,T92,T93
10CoveredT1,T2,T3
11CoveredT91,T92,T93

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT91,T92,T93
10CoveredT1,T2,T3
11CoveredT91,T92,T93

 LINE       1084
 EXPRESSION (sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | sw_ctrl_err.prog_err)
             ---------1--------   ---------2--------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT21
010CoveredT2,T25,T27
100CoveredT2,T5,T11

 LINE       1128
 EXPRESSION (intg_err | eflash_cmd_intg_err | tl_gate_intg_err | tl_prog_gate_intg_err)
             ----1---   ---------2---------   --------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT15,T16,T41
0010CoveredT15,T16,T41
0100CoveredT7,T23,T46
1000CoveredT15,T16,T41

 LINE       1136
 EXPRESSION (rd_cnt_err | prog_cnt_err)
             -----1----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T41
10CoveredT15,T16,T41

 LINE       1137
 EXPRESSION (flash_phy_rsp.fifo_err | adapter_fifo_err)
             -----------1----------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T41
10CoveredT15,T16,T41

 LINE       1142
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[0].q)) ? reg2hw.ecc_single_err_cnt[0].q : ((reg2hw.ecc_single_err_cnt[0].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T39,T94

 LINE       1142
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[1].q)) ? reg2hw.ecc_single_err_cnt[1].q : ((reg2hw.ecc_single_err_cnt[1].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T39,T94

 LINE       1400
 EXPRESSION (prog_op_valid | rd_op_valid | erase_op_valid)
             ------1------   -----2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T3,T10
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Toggle Coverage for Module : flash_ctrl
TotalCoveredPercent
Totals 122 111 90.98
Total Bits 2750 2707 98.44
Total Bits 0->1 1375 1354 98.47
Total Bits 1->0 1375 1353 98.40

Ports 122 111 90.98
Port Bits 2750 2707 98.44
Port Bits 0->1 1375 1354 98.47
Port Bits 1->0 1375 1353 98.40

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T17 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T2,T3,T17 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T17 Yes T1,T2,T3 INPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T3,T10,T5 Yes T1,T2,T3 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T3,T17,T10 Yes T1,T2,T3 INPUT
lc_iso_part_sw_rd_en_i[3:0] Yes Yes T3,T17,T10 Yes T1,T2,T3 INPUT
lc_iso_part_sw_wr_en_i[3:0] Yes Yes T3,T17,T10 Yes T1,T2,T3 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T3,T10,T55 Yes T3,T10,T55 INPUT
lc_escalate_en_i[0] No No Yes T42,T95,T96 INPUT
lc_escalate_en_i[1] No Yes *T11,*T14,*T42 No INPUT
lc_escalate_en_i[2] No No Yes T11,T42,T77 INPUT
lc_escalate_en_i[3] No Yes T11,T14,T42 No INPUT
lc_nvm_debug_en_i[3:0] Yes Yes T3,T55,T97 Yes T3,T18,T20 INPUT
core_tl_i.d_ready Yes Yes T2,T3,T17 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T1,T11,T14 Yes T1,T11,T14 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T17 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready Yes Yes T2,T3,T17 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T4,T11,T26 Yes T1,T4,T47 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T22,T14 Yes T1,T4,T26 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T4,T26,T57 Yes T4,T26,T59 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T4,T14,T54 Yes T4,T22,T47 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T4,T11,T26 Yes T4,T26,T54 INPUT
prim_tl_i.a_address[31:0] Yes Yes T4,T11,T22 Yes T1,T47,T98 INPUT
prim_tl_i.a_source[7:0] Yes Yes T22,T26,T47 Yes T4,T11,T14 INPUT
prim_tl_i.a_size[1:0] Yes Yes T1,T4,T57 Yes T4,T99,T36 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T1,T4,T11 Yes T4,T98,T59 INPUT
prim_tl_i.a_valid Yes Yes T65,T66,T100 Yes T65,T66,T100 INPUT
prim_tl_o.a_ready Yes Yes T65,T66,T100 Yes T65,T66,T100 OUTPUT
prim_tl_o.d_error Yes Yes T65,T100,T101 Yes T65,T100,T101 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T65,T66,T100 Yes T65,T66,T100 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes T65,*T66,T100 Yes T65,T66,T100 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T65,T66,T100 Yes T65,T66,T100 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T65,T66,T100 Yes T65,T66,T100 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T65,T66,T100 Yes T65,T66,T100 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T65,*T66,*T100 Yes T65,T66,T100 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T65,T66,T100 Yes T65,T66,T100 OUTPUT
mem_tl_i.d_ready Yes Yes T2,T3,T17 Yes T1,T2,T3 INPUT
mem_tl_i.a_user.data_intg[6:0] Yes Yes T4,T24,T6 Yes T4,T24,T6 INPUT
mem_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T4,T5 INPUT
mem_tl_i.a_user.instr_type[3:0] Yes Yes T4,T11,T24 Yes T4,T24,T6 INPUT
mem_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_data[31:0] Yes Yes T4,T24,T22 Yes T4,T24,T6 INPUT
mem_tl_i.a_mask[3:0] Yes Yes T4,T24,T6 Yes T4,T24,T6 INPUT
mem_tl_i.a_address[31:0] Yes Yes T4,T24,T6 Yes T4,T24,T6 INPUT
mem_tl_i.a_source[7:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
mem_tl_i.a_size[1:0] Yes Yes T4,T24,T6 Yes T4,T24,T6 INPUT
mem_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_opcode[2:0] Yes Yes T4,T24,T6 Yes T4,T24,T22 INPUT
mem_tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
mem_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T17 OUTPUT
mem_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
mem_tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mem_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
mem_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_source[7:0] Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
mem_tl_o.d_size[1:0] Yes Yes T65,T100,T101 Yes T65,T100,T101 OUTPUT
mem_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_opcode[0] Yes Yes *T46,*T65,*T100 Yes T46,T65,T100 OUTPUT
mem_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
otp_o.addr_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_o.data_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_i.seed_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_i.rand_key[127:0] Yes Yes T3,T4,T18 Yes T3,T4,T10 INPUT
otp_i.key[127:0] Yes Yes T3,T17,T4 Yes T1,T2,T3 INPUT
otp_i.addr_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_i.data_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rma_req_i[3:0] Yes Yes T10,T12,T59 Yes T10,T12,T59 INPUT
rma_seed_i[31:0] Yes Yes T59,T102,T103 Yes T12,T59,T102 INPUT
rma_ack_o[3:0] Yes Yes T69,T104,T105 Yes T59,T102,T106 OUTPUT
pwrmgr_o.flash_idle Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][2] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][3] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][4] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][5] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][6] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][7] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][8] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][9] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][10] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][11] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][12] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][13] Yes Yes T3,T4,T19 Yes T3,T4,T19 OUTPUT
keymgr_o.seeds[0][14] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][15] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][17] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][18] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][19] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][20] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][21] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][22] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][23] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][24] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][25] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][26] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][27] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][28] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][29] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][30] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][31] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][32] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][33] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][34] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][35] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][36] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][37] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][38] Yes Yes T3,T18,T20 Yes T3,T18,T20 OUTPUT
keymgr_o.seeds[0][39] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][40] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][41] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][42] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][43] Yes Yes T3,T4,T18 Yes T3,T4,T18 OUTPUT
keymgr_o.seeds[0][44] Yes Yes T3,T4,T19 Yes T3,T4,T19 OUTPUT
keymgr_o.seeds[0][45] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][46] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][47] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][48] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][49] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][50] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][51] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][52] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][53] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][54] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][55] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][56] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][57] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][58] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][59] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][60] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][61] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][62] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][63] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][64] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][65] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][66] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][67] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][68] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][69] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][70] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][71] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][72] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][73] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][74] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][75] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][76] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][77] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][78] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][79] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][80] Yes Yes T1,T3,T10 Yes T1,T3,T10 OUTPUT
keymgr_o.seeds[0][81] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][82] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][83] Yes Yes T3,T10,T19 Yes T3,T10,T19 OUTPUT
keymgr_o.seeds[0][84] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][85] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][86] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][87] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][88] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][89] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][90] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][91] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][92] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][93] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][94] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][95] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][96] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][97] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][98] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][99] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][100] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][101] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][102] Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT
keymgr_o.seeds[0][103] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][104] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][105] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][106] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][107] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][108] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][109] Yes Yes T1,T3,T18 Yes T1,T3,T18 OUTPUT
keymgr_o.seeds[0][110] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][111] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][112] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][113] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][114] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][115] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][116] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][117] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][118] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][119] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][120] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][121] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][122] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][123] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][124] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][125] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][126] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][127] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][128] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][129] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][130] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][131] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][132] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][133] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][134] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][135] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][136] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][137] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][138] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][139] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][140] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][141] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][142] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][143] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][144] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][145] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][146] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][147] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][148] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][149] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][150] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][151] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][152] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][153] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][154] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][155] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][156] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][157] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][158] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][159] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][160] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][161] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][162] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][163] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][164] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][165] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][166] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][167] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][168] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][169] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][170] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][171] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][172] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][173] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][174] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][175] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][176] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][177] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][178] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][179] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][180] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][181] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][182] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][184:183] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][185] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][186] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][187] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][188] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][189] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][190] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][191] Yes Yes T3,T4,T18 Yes T3,T4,T18 OUTPUT
keymgr_o.seeds[0][192] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][193] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][194] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][195] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][196] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][197] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][198] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][199] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][200] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][201] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][202] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][203] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][204] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][205] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][206] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][207] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][208] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][209] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][210] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][211] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][212] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][213] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][214] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][215] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][216] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][217] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][218] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][219] Yes Yes T3,T4,T55 Yes T3,T4,T55 OUTPUT
keymgr_o.seeds[0][220] Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT
keymgr_o.seeds[0][221] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][222] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][223] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][224] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][225] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][226] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][227] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][228] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][229] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][230] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][231] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][232] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][233] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][234] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][235] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][236] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][237] Yes Yes T3,T10,T18 Yes T3,T10,T18 OUTPUT
keymgr_o.seeds[0][238] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][239] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][240] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][241] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][242] Yes Yes T3,T4,T19 Yes T3,T4,T19 OUTPUT
keymgr_o.seeds[0][243] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][244] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][245] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][246] Yes Yes T1,T3,T10 Yes T1,T3,T10 OUTPUT
keymgr_o.seeds[0][247] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[0][248] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][249] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][250] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[0][251] Yes Yes T3,T4,T20 Yes T3,T4,T20 OUTPUT
keymgr_o.seeds[0][252] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[0][253] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][254] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[0][255] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][1] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][3] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][4] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][5] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][6] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][7] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][8] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][9] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][10] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][11] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][13:12] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][14] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][15] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][16] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][18] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][19] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][20] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][21] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][22] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][23] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][24] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][25] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][26] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][27] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][28] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][29] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][30] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][31] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][32] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][33] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][34] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][35] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][36] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][37] Yes Yes T2,T3,T10 Yes T2,T3,T10 OUTPUT
keymgr_o.seeds[1][38] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][39] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][40] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][41] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][42] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][44:43] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][45] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][46] Yes Yes T3,T4,T18 Yes T3,T4,T18 OUTPUT
keymgr_o.seeds[1][47] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][48] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][49] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][50] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][51] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][52] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][53] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][54] Yes Yes T3,T4,T18 Yes T3,T4,T18 OUTPUT
keymgr_o.seeds[1][55] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][56] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][57] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][58] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][59] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][60] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][61] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][62] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][63] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][64] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][65] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][66] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][67] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][68] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][69] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][70] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][71] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][72] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][73] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][74] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][75] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][76] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][77] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][78] Yes Yes T1,T3,T19 Yes T1,T3,T19 OUTPUT
keymgr_o.seeds[1][79] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][80] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][81] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][82] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][83] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][84] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][85] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][86] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][87] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][88] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][89] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][90] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][91] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][92] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][93] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][94] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][95] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][96] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][97] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][98] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][99] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][100] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][101] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][102] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][103] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][104] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][105] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][106] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][107] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][108] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][109] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][110] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][111] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][112] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][113] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][114] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][115] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][116] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][117] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][118] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][119] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][120] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][121] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][122] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][123] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][124] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][125] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][126] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][127] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][128] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][129] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][130] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][131] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][132] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][133] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][134] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][135] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][136] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][137] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][138] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][139] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][140] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][141] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][142] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][143] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][144] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][145] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][146] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][147] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][148] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][149] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][150] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][151] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][152] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][153] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][154] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][155] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][157:156] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][158] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][159] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][160] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][161] Yes Yes T3,T4,T18 Yes T3,T4,T18 OUTPUT
keymgr_o.seeds[1][162] Yes Yes T1,T3,T10 Yes T1,T3,T10 OUTPUT
keymgr_o.seeds[1][163] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][164] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][165] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][166] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][167] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][168] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][169] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][170] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][171] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][172] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][173] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][174] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][175] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][176] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][177] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][178] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][179] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][180] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][181] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][182] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][183] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][184] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][185] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][186] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][187] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][188] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][189] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][190] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][191] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][192] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][193] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][194] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][195] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][196] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][197] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][199:198] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][200] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][201] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][202] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][203] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][204] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][205] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][206] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][207] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][208] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][209] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][210] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][211] Yes Yes T3,T4,T19 Yes T3,T4,T19 OUTPUT
keymgr_o.seeds[1][212] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][213] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][214] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][215] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][216] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][217] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][218] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][219] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][220] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][221] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][222] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][223] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][224] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][225] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][226] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][227] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][228] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][229] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][230] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][231] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][232] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][233] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][234] Yes Yes T3,T4,T10 Yes T3,T4,T10 OUTPUT
keymgr_o.seeds[1][235] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][236] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][237] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][238] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][239] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][240] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][241] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][242] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][243] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][244] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][245] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][246] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][247] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][248] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][249] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][250] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][251] Yes Yes T2,T3,T17 Yes T2,T3,T17 OUTPUT
keymgr_o.seeds[1][252] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
keymgr_o.seeds[1][253] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
keymgr_o.seeds[1][254] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][255] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_tck_i No No No INPUT
cio_tms_i No No No INPUT
cio_tdi_i No No No INPUT
cio_tdo_en_o No No No OUTPUT
cio_tdo_o No No Yes T18,T107,T108 OUTPUT
intr_corr_err_o Yes Yes T2,T25,T27 Yes T2,T25,T27 OUTPUT
intr_prog_empty_o Yes Yes T2,T24,T26 Yes T2,T24,T26 OUTPUT
intr_prog_lvl_o Yes Yes T2,T24,T26 Yes T2,T24,T26 OUTPUT
intr_rd_full_o Yes Yes T33,T34,T35 Yes T33,T34,T35 OUTPUT
intr_rd_lvl_o Yes Yes T36,T37,T33 Yes T36,T37,T33 OUTPUT
intr_op_done_o Yes Yes T2,T24,T26 Yes T2,T24,T26 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T5,T11 Yes T2,T5,T11 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T10,T109,T91 Yes T10,T109,T91 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[2].ack_p Yes Yes T2,T5,T12 Yes T2,T5,T12 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[3].ack_p Yes Yes T91,T92,T93 Yes T91,T92,T93 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[4].ack_p Yes Yes T91,T92,T93 Yes T91,T92,T93 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T5,T11 Yes T2,T5,T11 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T10,T109,T91 Yes T10,T109,T91 OUTPUT
alert_tx_o[2].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_p Yes Yes T2,T5,T12 Yes T2,T5,T12 OUTPUT
alert_tx_o[3].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[3].alert_p Yes Yes T91,T92,T93 Yes T91,T92,T93 OUTPUT
alert_tx_o[4].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[4].alert_p Yes Yes T91,T92,T93 Yes T91,T92,T93 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
fla_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T1,T2,T3 Yes T2,T3,T17 INPUT
flash_power_ready_h_i Yes Yes T89,T81,T90 Yes T89,T81,T90 INPUT
flash_test_mode_a_io[1:0] No No No INOUT
flash_test_voltage_h_io No No No INOUT

*Tests covering at least one bit in the range

Branch Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 875 2 2 100.00
TERNARY 1142 2 2 100.00
TERNARY 1142 2 2 100.00
TERNARY 700 2 2 100.00
IF 630 2 2 100.00
CASE 751 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 875 (sw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1142 ((®2hw.ecc_single_err_cnt[0].q)) ?

Branches:
-1-StatusTests
1 Covered T22,T39,T94
0 Covered T1,T2,T3


LineNo. Expression -1-: 1142 ((®2hw.ecc_single_err_cnt[1].q)) ?

Branches:
-1-StatusTests
1 Covered T22,T39,T94
0 Covered T1,T2,T3


LineNo. Expression -1-: 700 (sw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 630 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 751 case (op_type)

Branches:
-1-StatusTests
FlashOpRead Covered T1,T2,T3
FlashOpProgram Covered T1,T2,T3
FlashOpErase Covered T1,T3,T10
default Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 70 70 100.00 59 84.29
Cover properties 0 0 0
Cover sequences 0 0 0
Total 70 70 100.00 59 84.29




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FifoDepthCheck_A 1043 1043 0 0
FlashAddrKnown_A 396141728 281190235 0 0
FlashAddrKnown_AKnownEnable 396141728 395279982 0 0
FlashKnownO_A 396141728 395279982 0 0
FlashProgKnown_A 396141728 163182785 0 0
FlashProgKnown_AKnownEnable 396141728 395279982 0 0
FpvSecCmAddrCntAlertCheck_A 396141728 50 0 0
FpvSecCmArbFsmCheck_A 396141728 50 0 0
FpvSecCmEflashReqFifoRptrCheck_A 396141728 0 0 0
FpvSecCmEflashReqFifoWptrCheck_A 396141728 0 0 0
FpvSecCmEflashRspFifoRptrCheck_A 396141728 0 0 0
FpvSecCmEflashRspFifoWptrCheck_A 396141728 0 0 0
FpvSecCmEflashSramReqFifoRptrCheck_A 396141728 0 0 0
FpvSecCmEflashSramReqFifoWptrCheck_A 396141728 0 0 0
FpvSecCmLcCtrlFsmCheck_A 396141728 50 0 0
FpvSecCmLcCtrlRmaFsmCheck_A 396141728 50 0 0
FpvSecCmPageCntAlertCheck_A 396141728 50 0 0
FpvSecCmProgCnt_A 396141728 50 0 0
FpvSecCmRdCnt_A 396141728 50 0 0
FpvSecCmRdReqFifoRptrCheck_A 396141728 0 0 0
FpvSecCmRdReqFifoWptrCheck_A 396141728 0 0 0
FpvSecCmRdRspFifoRptrCheck_A 396141728 50 0 0
FpvSecCmRdRspFifoWptrCheck_A 396141728 50 0 0
FpvSecCmRdSramReqFifoRptrCheck_A 396141728 0 0 0
FpvSecCmRdSramReqFifoWptrCheck_A 396141728 0 0 0
FpvSecCmRegWeOnehotCheck_A 396141728 50 0 0
FpvSecCmSeedCntAlertCheck_A 396141728 50 0 0
FpvSecCmTlLcGateFsm_A 396141728 50 0 0
FpvSecCmTlProgLcGateFsm_A 396141728 50 0 0
FpvSecCmWipeIdx_A 396141728 50 0 0
FpvSecCmWordCntAlertCheck_A 396141728 50 0 0
IntrErrO_A 396141728 395279982 0 0
IntrOpDoneKnownO_A 396141728 395279982 0 0
IntrProgEmptyKnownO_A 396141728 395279982 0 0
IntrProgLvlKnownO_A 396141728 395279982 0 0
IntrProgRdFullKnownO_A 396141728 395279982 0 0
IntrRdLvlKnownO_A 396141728 395279982 0 0
MemRspPayLoad_A 396141728 5211150 0 0
MemRspPayLoad_AKnownEnable 396141728 395279982 0 0
MemTlAReadyKnownO_A 396141728 395279982 0 0
MemTlDValidKnownO_A 396141728 395279982 0 0
PrimRspPayLoad_A 396141728 0 0 0
PrimRspPayLoad_AKnownEnable 396141728 395279982 0 0
PrimTlAReadyKnownO_A 396141728 395279982 0 0
PrimTlDValidKnownO_A 396141728 395279982 0 0
RspPayLoad_A 395700516 39276884 0 0
RspPayLoad_AKnownEnable 396141728 395279982 0 0
TdoEnIsOne_A 396141728 395279982 0 0
TdoKnown_A 396141728 395279982 0 0
TlAReadyKnownO_A 396141728 395279982 0 0
TlDValidKnownO_A 396141728 395279982 0 0
gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A 396141728 50 0 0
gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A 396141728 50 0 0
gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A 396141728 50 0 0
gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A 396141728 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A 396141728 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A 396141728 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A 396141728 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A 396141728 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A 396141728 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A 396141728 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A 396141728 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A 396141728 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A 396141728 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A 396141728 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A 396141728 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A 396141728 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A 396141728 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A 396141728 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 396141728 23 0 0


FifoDepthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1043 1043 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

FlashAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 281190235 0 0
T1 3942 1664 0 0
T2 1673 528 0 0
T3 257018 140107 0 0
T4 5011 909 0 0
T5 150570 126582 0 0
T10 394889 378528 0 0
T17 1404 344 0 0
T18 1350 160 0 0
T19 1741 344 0 0
T20 1263 160 0 0

FlashAddrKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

FlashKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

FlashProgKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 163182785 0 0
T1 3942 1046 0 0
T2 1673 66 0 0
T3 257018 42583 0 0
T4 5011 208 0 0
T5 150570 117579 0 0
T10 394889 218800 0 0
T17 1404 24 0 0
T18 1350 0 0 0
T19 1741 156 0 0
T20 1263 0 0 0
T44 0 210 0 0
T55 0 43074 0 0

FlashProgKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

FpvSecCmAddrCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmArbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmEflashReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmEflashReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmEflashRspFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmEflashRspFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmEflashSramReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmEflashSramReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmLcCtrlFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmLcCtrlRmaFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmPageCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmProgCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmRdCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmRdReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmRdReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmRdRspFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmRdRspFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmRdSramReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmRdSramReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmSeedCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmTlProgLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmWipeIdx_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

FpvSecCmWordCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

IntrErrO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

IntrOpDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

IntrProgEmptyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

IntrProgLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

IntrProgRdFullKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

IntrRdLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

MemRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 5211150 0 0
T1 3942 121 0 0
T2 1673 6 0 0
T3 257018 0 0 0
T4 5011 64 0 0
T5 150570 16293 0 0
T6 0 15 0 0
T10 394889 0 0 0
T17 1404 0 0 0
T18 1350 0 0 0
T19 1741 0 0 0
T20 1263 0 0 0
T22 0 16278 0 0
T24 0 22 0 0
T26 0 22 0 0
T38 0 55 0 0
T47 0 17033 0 0

MemRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

MemTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

MemTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

PrimRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 0 0 0

PrimRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

PrimTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

PrimTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

RspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 395700516 39276884 0 0
T1 3942 1090 0 0
T2 1673 461 0 0
T3 257018 33836 0 0
T4 5011 196 0 0
T5 150570 74380 0 0
T10 394889 85522 0 0
T17 1404 119 0 0
T18 1350 16 0 0
T19 1741 115 0 0
T20 1263 72 0 0

RspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

TdoEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

TdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 395279982 0 0
T1 3942 3879 0 0
T2 1673 1520 0 0
T3 257018 245809 0 0
T4 5011 4719 0 0
T5 150570 150474 0 0
T10 394889 394873 0 0
T17 1404 1267 0 0
T18 1350 1252 0 0
T19 1741 1648 0 0
T20 1263 1211 0 0

gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 50 0 0
T15 128115 10 0 0
T16 0 10 0 0
T41 0 10 0 0
T80 32000 0 0 0
T110 0 10 0 0
T111 0 10 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 396141728 23 0 0
T15 128115 6 0 0
T16 0 4 0 0
T41 0 4 0 0
T80 32000 0 0 0
T110 0 5 0 0
T111 0 4 0 0
T112 1200 0 0 0
T113 1110 0 0 0
T114 18505 0 0 0
T115 2582 0 0 0
T116 1059 0 0 0
T117 194075 0 0 0
T118 2621 0 0 0
T119 521 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%