Line Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Module :
flash_phy_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T11,T7 |
1 | 1 | Covered | T1,T2,T16 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T11,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T16 |
Branch Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T16 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T16 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763645586 |
6705014 |
0 |
0 |
T1 |
4994 |
83 |
0 |
0 |
T2 |
1157486 |
17580 |
0 |
0 |
T3 |
444042 |
0 |
0 |
0 |
T4 |
4308 |
0 |
0 |
0 |
T6 |
134094 |
23396 |
0 |
0 |
T7 |
0 |
47351 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T15 |
8596 |
0 |
0 |
0 |
T16 |
3972 |
45 |
0 |
0 |
T17 |
3530 |
0 |
0 |
0 |
T18 |
1414 |
2 |
0 |
0 |
T19 |
6142 |
0 |
0 |
0 |
T22 |
0 |
22275 |
0 |
0 |
T23 |
0 |
42597 |
0 |
0 |
T33 |
0 |
23409 |
0 |
0 |
T34 |
0 |
42481 |
0 |
0 |
T62 |
0 |
8518 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763645586 |
762049374 |
0 |
0 |
T1 |
4994 |
4666 |
0 |
0 |
T2 |
1157486 |
1157162 |
0 |
0 |
T3 |
444042 |
443720 |
0 |
0 |
T4 |
4308 |
4116 |
0 |
0 |
T6 |
134094 |
133852 |
0 |
0 |
T15 |
8596 |
7172 |
0 |
0 |
T16 |
3972 |
3638 |
0 |
0 |
T17 |
3530 |
3232 |
0 |
0 |
T18 |
1414 |
1266 |
0 |
0 |
T19 |
6142 |
6004 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763645586 |
6705025 |
0 |
0 |
T1 |
4994 |
83 |
0 |
0 |
T2 |
1157486 |
17580 |
0 |
0 |
T3 |
444042 |
0 |
0 |
0 |
T4 |
4308 |
0 |
0 |
0 |
T6 |
134094 |
23396 |
0 |
0 |
T7 |
0 |
47351 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T15 |
8596 |
0 |
0 |
0 |
T16 |
3972 |
45 |
0 |
0 |
T17 |
3530 |
0 |
0 |
0 |
T18 |
1414 |
2 |
0 |
0 |
T19 |
6142 |
0 |
0 |
0 |
T22 |
0 |
22275 |
0 |
0 |
T23 |
0 |
42597 |
0 |
0 |
T33 |
0 |
23409 |
0 |
0 |
T34 |
0 |
42481 |
0 |
0 |
T62 |
0 |
8518 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763645587 |
16359261 |
0 |
0 |
T1 |
4994 |
147 |
0 |
0 |
T2 |
1157486 |
17621 |
0 |
0 |
T3 |
444042 |
64 |
0 |
0 |
T4 |
4308 |
32 |
0 |
0 |
T6 |
134094 |
23460 |
0 |
0 |
T7 |
0 |
23284 |
0 |
0 |
T15 |
8596 |
256 |
0 |
0 |
T16 |
3972 |
109 |
0 |
0 |
T17 |
3530 |
64 |
0 |
0 |
T18 |
1414 |
34 |
0 |
0 |
T19 |
6142 |
32 |
0 |
0 |
T22 |
0 |
8087 |
0 |
0 |
T23 |
0 |
19362 |
0 |
0 |
T28 |
0 |
131072 |
0 |
0 |
T34 |
0 |
22673 |
0 |
0 |
T62 |
0 |
8518 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T11,T7,T23 |
1 | 1 | Covered | T1,T2,T16 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T11,T7,T23 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T16 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T16 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T16 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822793 |
3694579 |
0 |
0 |
T1 |
2497 |
61 |
0 |
0 |
T2 |
578743 |
9527 |
0 |
0 |
T3 |
222021 |
0 |
0 |
0 |
T4 |
2154 |
0 |
0 |
0 |
T6 |
67047 |
14657 |
0 |
0 |
T7 |
0 |
24067 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T15 |
4298 |
0 |
0 |
0 |
T16 |
1986 |
42 |
0 |
0 |
T17 |
1765 |
0 |
0 |
0 |
T18 |
707 |
2 |
0 |
0 |
T19 |
3071 |
0 |
0 |
0 |
T22 |
0 |
14188 |
0 |
0 |
T23 |
0 |
23235 |
0 |
0 |
T34 |
0 |
19808 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822793 |
381024687 |
0 |
0 |
T1 |
2497 |
2333 |
0 |
0 |
T2 |
578743 |
578581 |
0 |
0 |
T3 |
222021 |
221860 |
0 |
0 |
T4 |
2154 |
2058 |
0 |
0 |
T6 |
67047 |
66926 |
0 |
0 |
T15 |
4298 |
3586 |
0 |
0 |
T16 |
1986 |
1819 |
0 |
0 |
T17 |
1765 |
1616 |
0 |
0 |
T18 |
707 |
633 |
0 |
0 |
T19 |
3071 |
3002 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822793 |
3694587 |
0 |
0 |
T1 |
2497 |
61 |
0 |
0 |
T2 |
578743 |
9527 |
0 |
0 |
T3 |
222021 |
0 |
0 |
0 |
T4 |
2154 |
0 |
0 |
0 |
T6 |
67047 |
14657 |
0 |
0 |
T7 |
0 |
24067 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T15 |
4298 |
0 |
0 |
0 |
T16 |
1986 |
42 |
0 |
0 |
T17 |
1765 |
0 |
0 |
0 |
T18 |
707 |
2 |
0 |
0 |
T19 |
3071 |
0 |
0 |
0 |
T22 |
0 |
14188 |
0 |
0 |
T23 |
0 |
23235 |
0 |
0 |
T34 |
0 |
19808 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822794 |
8839222 |
0 |
0 |
T1 |
2497 |
125 |
0 |
0 |
T2 |
578743 |
9568 |
0 |
0 |
T3 |
222021 |
64 |
0 |
0 |
T4 |
2154 |
32 |
0 |
0 |
T6 |
67047 |
14721 |
0 |
0 |
T15 |
4298 |
256 |
0 |
0 |
T16 |
1986 |
106 |
0 |
0 |
T17 |
1765 |
64 |
0 |
0 |
T18 |
707 |
34 |
0 |
0 |
T19 |
3071 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T28,T32,T132 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T16 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T33 |
1 | 1 | Covered | T1,T2,T16 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T16 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T7,T33 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T16 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T16 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T16 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T16 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822793 |
3010435 |
0 |
0 |
T1 |
2497 |
22 |
0 |
0 |
T2 |
578743 |
8053 |
0 |
0 |
T3 |
222021 |
0 |
0 |
0 |
T4 |
2154 |
0 |
0 |
0 |
T6 |
67047 |
8739 |
0 |
0 |
T7 |
0 |
23284 |
0 |
0 |
T15 |
4298 |
0 |
0 |
0 |
T16 |
1986 |
3 |
0 |
0 |
T17 |
1765 |
0 |
0 |
0 |
T18 |
707 |
0 |
0 |
0 |
T19 |
3071 |
0 |
0 |
0 |
T22 |
0 |
8087 |
0 |
0 |
T23 |
0 |
19362 |
0 |
0 |
T33 |
0 |
23409 |
0 |
0 |
T34 |
0 |
22673 |
0 |
0 |
T62 |
0 |
8518 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822793 |
381024687 |
0 |
0 |
T1 |
2497 |
2333 |
0 |
0 |
T2 |
578743 |
578581 |
0 |
0 |
T3 |
222021 |
221860 |
0 |
0 |
T4 |
2154 |
2058 |
0 |
0 |
T6 |
67047 |
66926 |
0 |
0 |
T15 |
4298 |
3586 |
0 |
0 |
T16 |
1986 |
1819 |
0 |
0 |
T17 |
1765 |
1616 |
0 |
0 |
T18 |
707 |
633 |
0 |
0 |
T19 |
3071 |
3002 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822793 |
3010438 |
0 |
0 |
T1 |
2497 |
22 |
0 |
0 |
T2 |
578743 |
8053 |
0 |
0 |
T3 |
222021 |
0 |
0 |
0 |
T4 |
2154 |
0 |
0 |
0 |
T6 |
67047 |
8739 |
0 |
0 |
T7 |
0 |
23284 |
0 |
0 |
T15 |
4298 |
0 |
0 |
0 |
T16 |
1986 |
3 |
0 |
0 |
T17 |
1765 |
0 |
0 |
0 |
T18 |
707 |
0 |
0 |
0 |
T19 |
3071 |
0 |
0 |
0 |
T22 |
0 |
8087 |
0 |
0 |
T23 |
0 |
19362 |
0 |
0 |
T33 |
0 |
23409 |
0 |
0 |
T34 |
0 |
22673 |
0 |
0 |
T62 |
0 |
8518 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381822793 |
7520039 |
0 |
0 |
T1 |
2497 |
22 |
0 |
0 |
T2 |
578743 |
8053 |
0 |
0 |
T3 |
222021 |
0 |
0 |
0 |
T4 |
2154 |
0 |
0 |
0 |
T6 |
67047 |
8739 |
0 |
0 |
T7 |
0 |
23284 |
0 |
0 |
T15 |
4298 |
0 |
0 |
0 |
T16 |
1986 |
3 |
0 |
0 |
T17 |
1765 |
0 |
0 |
0 |
T18 |
707 |
0 |
0 |
0 |
T19 |
3071 |
0 |
0 |
0 |
T22 |
0 |
8087 |
0 |
0 |
T23 |
0 |
19362 |
0 |
0 |
T28 |
0 |
131072 |
0 |
0 |
T34 |
0 |
22673 |
0 |
0 |
T62 |
0 |
8518 |
0 |
0 |