Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.82	100.00	91.27			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.43	100.00	89.74			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.76	100.00	91.05			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.43	100.00	89.74			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.95	97.64	92.91	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	97.75	92.45		100.00	93.48	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.76	100.00	91.05			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.05	97.64	93.40	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.38	96.63	83.96		100.00	91.30	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	458	418	91.27
Logical	458	418	91.27
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-787	91.63
790-794	81.25

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T33,T31
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T16,T7

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	763645586	1582250	0	0
ExclusiveOps_A	763645586	762049374	0	0
ExclusiveProgHazard_A	763645586	762049374	0	0
ExclusiveState_A	763645586	762049374	0	0
ForwardCheck_A	763645586	3832843	0	0
IdleCheck_A	763645586	100314840	0	0
MaxBufs_A	2078	2078	0	0
OneHotAlloc_A	763645586	762049374	0	0
OneHotMatch_A	763645586	762049374	0	0
OneHotRspMatch_A	763645586	762049374	0	0
OneHotUpdate_A	763645586	762049374	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	1582250	0	0
T1	4994	33	0	0
T2	1157486	438	0	0
T3	444042	0	0	0
T4	4308	0	0	0
T6	134094	2924	0	0
T7	0	2440	0	0
T11	0	2	0	0
T15	8596	0	0	0
T16	3972	20	0	0
T17	3530	0	0	0
T18	1414	0	0	0
T19	6142	0	0	0
T22	0	2496	0	0
T23	0	12278	0	0
T31	0	8	0	0
T33	0	936	0	0
T34	0	12401	0	0
T62	0	2244	0	0
T69	0	1235	0	0
T85	0	2319	0	0
T196	0	689	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	762049374	0	0
T1	4994	4666	0	0
T2	1157486	1157162	0	0
T3	444042	443720	0	0
T4	4308	4116	0	0
T6	134094	133852	0	0
T15	8596	7172	0	0
T16	3972	3638	0	0
T17	3530	3232	0	0
T18	1414	1266	0	0
T19	6142	6004	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	762049374	0	0
T1	4994	4666	0	0
T2	1157486	1157162	0	0
T3	444042	443720	0	0
T4	4308	4116	0	0
T6	134094	133852	0	0
T15	8596	7172	0	0
T16	3972	3638	0	0
T17	3530	3232	0	0
T18	1414	1266	0	0
T19	6142	6004	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	762049374	0	0
T1	4994	4666	0	0
T2	1157486	1157162	0	0
T3	444042	443720	0	0
T4	4308	4116	0	0
T6	134094	133852	0	0
T15	8596	7172	0	0
T16	3972	3638	0	0
T17	3530	3232	0	0
T18	1414	1266	0	0
T19	6142	6004	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	3832843	0	0
T2	1157486	17142	0	0
T3	444042	0	0	0
T4	4308	0	0	0
T5	286108	0	0	0
T6	134094	0	0	0
T7	0	44323	0	0
T15	8596	0	0	0
T16	3972	13	0	0
T17	3530	0	0	0
T18	1414	0	0	0
T19	6142	0	0	0
T23	0	30319	0	0
T31	0	57	0	0
T33	0	43933	0	0
T34	0	30080	0	0
T50	0	64	0	0
T62	0	12525	0	0
T69	0	8470	0	0
T185	0	16747	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	100314840	0	0
T1	4994	489	0	0
T2	1157486	876846	0	0
T3	444042	256	0	0
T4	4308	128	0	0
T6	134094	77208	0	0
T7	0	86500	0	0
T15	8596	1024	0	0
T16	3972	350	0	0
T17	3530	256	0	0
T18	1414	136	0	0
T19	6142	128	0	0
T22	0	29694	0	0
T23	0	725712	0	0
T28	0	524288	0	0
T34	0	810773	0	0
T62	0	18552	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2078	2078	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T6	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	762049374	0	0
T1	4994	4666	0	0
T2	1157486	1157162	0	0
T3	444042	443720	0	0
T4	4308	4116	0	0
T6	134094	133852	0	0
T15	8596	7172	0	0
T16	3972	3638	0	0
T17	3530	3232	0	0
T18	1414	1266	0	0
T19	6142	6004	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	762049374	0	0
T1	4994	4666	0	0
T2	1157486	1157162	0	0
T3	444042	443720	0	0
T4	4308	4116	0	0
T6	134094	133852	0	0
T15	8596	7172	0	0
T16	3972	3638	0	0
T17	3530	3232	0	0
T18	1414	1266	0	0
T19	6142	6004	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	762049374	0	0
T1	4994	4666	0	0
T2	1157486	1157162	0	0
T3	444042	443720	0	0
T4	4308	4116	0	0
T6	134094	133852	0	0
T15	8596	7172	0	0
T16	3972	3638	0	0
T17	3530	3232	0	0
T18	1414	1266	0	0
T19	6142	6004	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763645586	762049374	0	0
T1	4994	4666	0	0
T2	1157486	1157162	0	0
T3	444042	443720	0	0
T4	4308	4116	0	0
T6	134094	133852	0	0
T15	8596	7172	0	0
T16	3972	3638	0	0
T17	3530	3232	0	0
T18	1414	1266	0	0
T19	6142	6004	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	458	411	89.74
Logical	458	411	89.74
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	90.11
790-794	76.92

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T35,T44
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T33,T31
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T16,T7

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T133
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	381822793	957281	0	0
ExclusiveOps_A	381822793	381024687	0	0
ExclusiveProgHazard_A	381822793	381024687	0	0
ExclusiveState_A	381822793	381024687	0	0
ForwardCheck_A	381822793	2168212	0	0
IdleCheck_A	381822793	52206678	0	0
MaxBufs_A	1039	1039	0	0
OneHotAlloc_A	381822793	381024687	0	0
OneHotMatch_A	381822793	381024687	0	0
OneHotRspMatch_A	381822793	381024687	0	0
OneHotUpdate_A	381822793	381024687	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	957281	0	0
T1	2497	27	0	0
T2	578743	437	0	0
T3	222021	0	0	0
T4	2154	0	0	0
T6	67047	2924	0	0
T7	0	1400	0	0
T11	0	2	0	0
T15	4298	0	0	0
T16	1986	20	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T22	0	2496	0	0
T23	0	7043	0	0
T34	0	5490	0	0
T62	0	2244	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	2168212	0	0
T2	578743	9090	0	0
T3	222021	0	0	0
T4	2154	0	0	0
T5	143054	0	0	0
T6	67047	0	0	0
T7	0	22250	0	0
T15	4298	0	0	0
T16	1986	11	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T23	0	16192	0	0
T31	0	51	0	0
T33	0	21740	0	0
T34	0	14318	0	0
T62	0	5042	0	0
T69	0	8470	0	0
T185	0	8183	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	52206678	0	0
T1	2497	419	0	0
T2	578743	466193	0	0
T3	222021	256	0	0
T4	2154	128	0	0
T6	67047	45072	0	0
T15	4298	1024	0	0
T16	1986	342	0	0
T17	1765	256	0	0
T18	707	136	0	0
T19	3071	128	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	458	417	91.05
Logical	458	417	91.05
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	91.24
790-794	84.62

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T151,T45
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T16,T6
0	1	Covered	T7,T33,T31
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T16,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T16,T7

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T16,T7
0	1	Covered	T1,T16,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T151,T45
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T16,T6
0	0	1	Covered	T1,T16,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	381822793	624969	0	0
ExclusiveOps_A	381822793	381024687	0	0
ExclusiveProgHazard_A	381822793	381024687	0	0
ExclusiveState_A	381822793	381024687	0	0
ForwardCheck_A	381822793	1664631	0	0
IdleCheck_A	381822793	48108162	0	0
MaxBufs_A	1039	1039	0	0
OneHotAlloc_A	381822793	381024687	0	0
OneHotMatch_A	381822793	381024687	0	0
OneHotRspMatch_A	381822793	381024687	0	0
OneHotUpdate_A	381822793	381024687	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	624969	0	0
T1	2497	6	0	0
T2	578743	1	0	0
T3	222021	0	0	0
T4	2154	0	0	0
T6	67047	0	0	0
T7	0	1040	0	0
T15	4298	0	0	0
T16	1986	0	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T23	0	5235	0	0
T31	0	8	0	0
T33	0	936	0	0
T34	0	6911	0	0
T69	0	1235	0	0
T85	0	2319	0	0
T196	0	689	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	1664631	0	0
T2	578743	8052	0	0
T3	222021	0	0	0
T4	2154	0	0	0
T5	143054	0	0	0
T6	67047	0	0	0
T7	0	22073	0	0
T15	4298	0	0	0
T16	1986	2	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T23	0	14127	0	0
T31	0	6	0	0
T33	0	22193	0	0
T34	0	15762	0	0
T50	0	64	0	0
T62	0	7483	0	0
T185	0	8564	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	48108162	0	0
T1	2497	70	0	0
T2	578743	410653	0	0
T3	222021	0	0	0
T4	2154	0	0	0
T6	67047	32136	0	0
T7	0	86500	0	0
T15	4298	0	0	0
T16	1986	8	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T22	0	29694	0	0
T23	0	725712	0	0
T28	0	524288	0	0
T34	0	810773	0	0
T62	0	18552	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0