Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	384864419	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	384864419	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	384864419	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	384864419	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	384864419	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	384864419	0	0	1037
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	384864419	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	384864419	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	384864419	0	0	1037
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	384864419	0	0	1037
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	384864419	0	0	1037
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	384864419	0	0	1037
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	384864419	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	384864419	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	384864419	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	384864419	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	384864419	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	384864419	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	384864419	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	384864419	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1042	1042	0	0
tb.dut.FlashAddrKnown_A	0	0	384864419	262468436	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	384864419	384030817	0	0
tb.dut.FlashKnownO_A	0	0	384864419	384030817	0	0
tb.dut.FlashProgKnown_A	0	0	384864419	159152626	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	384864419	384030817	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	384864419	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	384864419	50	0	0
tb.dut.IntrErrO_A	0	0	384864419	384030817	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	384864419	384030817	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	384864419	384030817	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	384864419	384030817	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	384864419	384030817	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	384864419	384030817	0	0
tb.dut.MemRspPayLoad_A	0	0	384864419	6241768	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	384864419	384030817	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	384864419	384030817	0	0
tb.dut.MemTlDValidKnownO_A	0	0	384864419	384030817	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	384864419	384030817	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	384864419	384030817	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	384864419	384030817	0	0
tb.dut.RspPayLoad_A	0	0	384653986	41721421	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	384864419	384030817	0	0
tb.dut.TdoEnIsOne_A	0	0	384864419	384030817	0	0
tb.dut.TdoKnown_A	0	0	384864419	384030817	0	0
tb.dut.TlAReadyKnownO_A	0	0	384864419	384030817	0	0
tb.dut.TlDValidKnownO_A	0	0	384864419	384030817	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	387235479	4042	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	387235479	1090	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	387235479	1471	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	387235479	1395	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	387235479	1111	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	387235479	1606	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	387235479	1473	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	387235479	1570	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	387235479	976	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	387235479	1683	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	387235479	1291	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	387235479	962	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	387235479	977	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	387235479	621	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	387235479	1020	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	387235479	1107	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	387235479	1024	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	387235479	1072	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	387235479	959	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	387235479	588	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	387235479	1095	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	387235479	1112	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	387235479	814	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	387235479	1033	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	387235479	955	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	387235479	1551	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	387235479	1042	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	387235479	1041	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	387235479	1477	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	387235479	1467	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	387235479	1686	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	387235479	1624	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	387235479	1620	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	387235479	1419	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	387235479	948	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	387235479	957	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	387235479	1553	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	387235479	1683	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	387235479	1039	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	387235479	970	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	387235479	970	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	387235479	602	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	387235479	1002	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	387235479	1014	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	387235479	1079	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	387235479	1037	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	387235479	548	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	387235479	1040	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	387235479	1104	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	387235479	532	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	387235479	1097	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	387235479	1519	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	387235479	1107	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	387235479	698	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	387235479	1163	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	387235479	1470	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	387235479	1028	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	387235479	1146	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	387235479	654	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	387235479	1118	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	387235479	1449	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	387235479	1106	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	387235479	1069	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	387235479	603	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	387235479	1117	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	387235479	1089	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	387235479	1097	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	387235479	1083	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	387235479	1067	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	387235479	1375	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	387235479	1476	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	387235479	1628	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	387235479	1503	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	387235479	1418	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	387235479	1437	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	387235479	1497	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	387235479	1482	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	387235479	753	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	387235479	573	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	387235479	1002	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	387235479	1083	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	387235479	938	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	387235479	1044	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	387235479	999	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	387235479	1002	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	387235479	580	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	387235479	971	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	384864419	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	384864419	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	384864419	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	384864419	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	384864419	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	384864419	23	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	387235379	31777092	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	387235379	386330002	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	387235379	386330002	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	387235379	42351513	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	387235379	386330002	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	387235379	386330002	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
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tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
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tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0

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