Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.26 95.71 93.88 98.31 92.52 98.23 96.99 98.18


Total tests in report: 1257
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.73 61.73 86.89 86.89 67.43 67.43 47.98 47.98 38.78 38.78 84.53 84.53 82.04 82.04 24.48 24.48 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.1612559986
67.88 6.15 87.67 0.78 69.05 1.62 51.49 3.52 48.30 9.52 85.53 1.00 83.01 0.97 50.12 25.65 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3528660536
72.83 4.94 90.71 3.03 75.03 5.98 53.74 2.25 48.30 0.00 91.25 5.72 83.88 0.87 66.86 16.74 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3926675611
77.75 4.93 91.13 0.42 75.34 0.30 74.22 20.48 60.54 12.24 92.00 0.75 83.98 0.10 67.05 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.1605897277
80.88 3.13 92.84 1.72 80.71 5.37 80.47 6.25 65.99 5.44 93.09 1.09 84.08 0.10 69.02 1.97 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3021526
83.04 2.15 93.12 0.28 85.93 5.22 82.72 2.25 65.99 0.00 93.68 0.60 84.56 0.49 75.28 6.26 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2254039376
85.08 2.04 93.12 0.00 86.11 0.18 82.72 0.00 65.99 0.00 93.68 0.00 92.82 8.25 81.10 5.83 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1974628987
86.61 1.54 93.30 0.18 86.95 0.85 86.73 4.02 67.35 1.36 94.45 0.77 96.12 3.30 81.38 0.28 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.357124265
88.12 1.51 93.90 0.61 87.64 0.69 88.79 2.06 73.47 6.12 95.09 0.64 96.31 0.19 81.66 0.28 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.13610981
89.22 1.09 94.16 0.26 88.15 0.50 94.19 5.40 74.15 0.68 95.54 0.45 96.31 0.00 82.03 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.473225181
90.13 0.91 94.40 0.24 88.46 0.31 94.23 0.05 79.59 5.44 95.84 0.30 96.31 0.00 82.06 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.1134585009
90.66 0.53 94.41 0.01 89.16 0.70 94.72 0.48 79.59 0.00 95.95 0.11 96.41 0.10 84.37 2.31 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.2205373744
91.17 0.51 94.41 0.00 89.27 0.10 95.26 0.55 82.31 2.72 95.95 0.00 96.41 0.00 84.56 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1752541163
91.60 0.44 94.41 0.00 89.32 0.05 95.26 0.00 82.31 0.00 95.95 0.00 96.41 0.00 87.58 3.02 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1329195475
91.97 0.36 94.46 0.04 89.37 0.06 95.49 0.22 84.35 2.04 96.05 0.11 96.41 0.00 87.64 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3746254650
92.30 0.33 95.13 0.68 89.52 0.14 95.49 0.00 84.35 0.00 97.50 1.45 96.41 0.00 87.70 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3350352011
92.60 0.30 95.14 0.01 89.53 0.01 95.52 0.03 86.39 2.04 97.55 0.04 96.41 0.00 87.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1508337175
92.90 0.29 95.23 0.09 90.26 0.73 96.31 0.79 86.39 0.00 97.55 0.00 96.41 0.00 88.13 0.43 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1832930507
93.14 0.24 95.35 0.12 90.27 0.01 96.31 0.00 86.39 0.00 97.55 0.00 96.41 0.00 89.70 1.57 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2154292524
93.34 0.20 95.35 0.01 90.29 0.02 96.31 0.00 87.76 1.36 97.57 0.02 96.41 0.00 89.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.1880680649
93.53 0.19 95.36 0.01 90.35 0.07 96.34 0.03 87.76 0.00 97.59 0.02 96.41 0.00 90.94 1.23 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1169691074
93.71 0.17 95.36 0.00 90.58 0.23 96.34 0.00 87.76 0.00 97.59 0.00 96.41 0.00 91.92 0.99 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2239662731
93.87 0.16 95.43 0.06 90.79 0.21 96.34 0.00 88.44 0.68 97.74 0.15 96.41 0.00 91.95 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3191564678
94.01 0.14 95.48 0.05 90.91 0.11 96.69 0.35 88.44 0.00 97.87 0.13 96.41 0.00 92.29 0.34 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.4267884201
94.15 0.14 95.48 0.00 90.96 0.06 96.88 0.19 89.12 0.68 97.89 0.02 96.41 0.00 92.32 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.212408297
94.29 0.14 95.51 0.03 91.22 0.26 97.09 0.21 89.12 0.00 97.99 0.11 96.41 0.00 92.69 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.4067499614
94.43 0.14 95.52 0.02 91.28 0.06 97.12 0.03 89.12 0.00 98.04 0.04 96.41 0.00 93.50 0.80 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.610524545
94.55 0.13 95.56 0.04 92.10 0.82 97.12 0.00 89.12 0.00 98.04 0.00 96.41 0.00 93.53 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3917946053
94.67 0.12 95.66 0.10 92.20 0.10 97.57 0.45 89.12 0.00 98.04 0.00 96.41 0.00 93.71 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.1715955169
94.79 0.12 95.66 0.00 92.26 0.06 97.64 0.06 89.80 0.68 98.06 0.02 96.41 0.00 93.71 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3497927998
94.89 0.10 95.66 0.00 92.26 0.00 97.64 0.00 90.48 0.68 98.06 0.00 96.41 0.00 93.74 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1949165490
94.99 0.10 95.66 0.00 92.27 0.01 97.64 0.00 91.16 0.68 98.06 0.00 96.41 0.00 93.74 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.949156795
95.09 0.10 95.66 0.00 92.27 0.00 97.64 0.00 91.84 0.68 98.06 0.00 96.41 0.00 93.74 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2654849227
95.18 0.10 95.66 0.00 92.27 0.00 97.64 0.00 92.52 0.68 98.06 0.00 96.41 0.00 93.74 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1008857270
95.26 0.08 95.66 0.00 92.39 0.12 97.70 0.06 92.52 0.00 98.06 0.00 96.41 0.00 94.11 0.37 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.4017585377
95.33 0.06 95.66 0.00 92.45 0.06 97.74 0.03 92.52 0.00 98.06 0.00 96.41 0.00 94.45 0.34 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.4247874890
95.38 0.06 95.66 0.00 92.67 0.22 97.74 0.00 92.52 0.00 98.10 0.04 96.50 0.10 94.48 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.2895480604
95.44 0.06 95.66 0.00 92.67 0.00 97.74 0.00 92.52 0.00 98.10 0.00 96.89 0.39 94.48 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.972727606
95.49 0.05 95.66 0.00 92.71 0.04 97.75 0.02 92.52 0.00 98.10 0.00 96.89 0.00 94.79 0.31 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.1161127358
95.54 0.05 95.66 0.00 92.71 0.00 97.75 0.00 92.52 0.00 98.10 0.00 96.89 0.00 95.13 0.34 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3349911098
95.57 0.04 95.66 0.00 92.78 0.08 97.82 0.06 92.52 0.00 98.10 0.00 96.89 0.00 95.25 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.980891757
95.61 0.03 95.66 0.00 92.82 0.04 97.82 0.00 92.52 0.00 98.10 0.00 96.89 0.00 95.44 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.1160675972
95.64 0.03 95.66 0.00 92.82 0.00 97.82 0.00 92.52 0.00 98.10 0.00 96.89 0.00 95.65 0.22 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4060371107
95.67 0.03 95.66 0.00 92.85 0.03 97.94 0.13 92.52 0.00 98.12 0.02 96.89 0.00 95.68 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1096929081
95.70 0.03 95.66 0.00 92.87 0.02 97.94 0.00 92.52 0.00 98.12 0.00 96.99 0.10 95.78 0.09 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1933522914
95.73 0.03 95.66 0.00 92.89 0.02 97.94 0.00 92.52 0.00 98.12 0.00 96.99 0.00 95.96 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3108941508
95.75 0.02 95.66 0.00 92.91 0.02 97.94 0.00 92.52 0.00 98.12 0.00 96.99 0.00 96.12 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1096731733
95.77 0.02 95.66 0.00 92.91 0.00 97.94 0.00 92.52 0.00 98.12 0.00 96.99 0.00 96.27 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1851030246
95.79 0.02 95.66 0.00 92.91 0.00 97.94 0.00 92.52 0.00 98.12 0.00 96.99 0.00 96.42 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.3577654284
95.81 0.02 95.66 0.00 92.93 0.03 97.98 0.03 92.52 0.00 98.14 0.02 96.99 0.00 96.49 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.4143545371
95.84 0.02 95.66 0.00 92.95 0.02 98.01 0.03 92.52 0.00 98.14 0.00 96.99 0.00 96.58 0.09 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.4238363505
95.86 0.02 95.66 0.00 92.97 0.02 98.01 0.00 92.52 0.00 98.14 0.00 96.99 0.00 96.70 0.12 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.1573042214
95.88 0.02 95.66 0.00 93.05 0.08 98.01 0.00 92.52 0.00 98.14 0.00 96.99 0.00 96.76 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.721323699
95.89 0.02 95.66 0.00 93.13 0.09 98.01 0.00 92.52 0.00 98.14 0.00 96.99 0.00 96.79 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4124114682
95.91 0.02 95.66 0.00 93.15 0.02 98.07 0.06 92.52 0.00 98.14 0.00 96.99 0.00 96.82 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2081937023
95.92 0.02 95.66 0.00 93.23 0.08 98.10 0.03 92.52 0.00 98.14 0.00 96.99 0.00 96.82 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3342997876
95.94 0.01 95.66 0.00 93.27 0.04 98.14 0.03 92.52 0.00 98.14 0.00 96.99 0.00 96.86 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3431574599
95.95 0.01 95.66 0.00 93.27 0.00 98.23 0.10 92.52 0.00 98.14 0.00 96.99 0.00 96.86 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2851924403
95.97 0.01 95.66 0.00 93.27 0.00 98.23 0.00 92.52 0.00 98.14 0.00 96.99 0.00 96.95 0.09 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.168500779
95.98 0.01 95.66 0.00 93.27 0.00 98.23 0.00 92.52 0.00 98.14 0.00 96.99 0.00 97.04 0.09 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.2518445606
95.99 0.01 95.70 0.04 93.27 0.00 98.25 0.02 92.52 0.00 98.14 0.00 96.99 0.00 97.07 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3318614938
96.00 0.01 95.70 0.00 93.33 0.06 98.25 0.00 92.52 0.00 98.14 0.00 96.99 0.00 97.10 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.1759847255
96.01 0.01 95.70 0.00 93.33 0.01 98.31 0.06 92.52 0.00 98.14 0.00 96.99 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1287486244
96.02 0.01 95.70 0.00 93.38 0.05 98.31 0.00 92.52 0.00 98.17 0.02 96.99 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2838814497
96.03 0.01 95.70 0.00 93.42 0.04 98.31 0.00 92.52 0.00 98.17 0.00 96.99 0.00 97.13 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.557540390
96.04 0.01 95.70 0.00 93.49 0.07 98.31 0.00 92.52 0.00 98.17 0.00 96.99 0.00 97.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.817066798
96.05 0.01 95.70 0.00 93.50 0.01 98.31 0.00 92.52 0.00 98.19 0.02 96.99 0.00 97.16 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3576080104
96.06 0.01 95.70 0.00 93.51 0.01 98.31 0.00 92.52 0.00 98.21 0.02 96.99 0.00 97.19 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3439657031
96.07 0.01 95.70 0.00 93.51 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.26 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2240609280
96.08 0.01 95.70 0.00 93.51 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.32 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2294561024
96.09 0.01 95.70 0.00 93.51 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.38 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.4243377651
96.10 0.01 95.70 0.00 93.51 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.44 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.4248871306
96.11 0.01 95.70 0.00 93.51 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.50 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.534048183
96.11 0.01 95.70 0.00 93.51 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.56 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.1739228808
96.12 0.01 95.70 0.00 93.56 0.06 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.56 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1099058125
96.13 0.01 95.70 0.00 93.61 0.05 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.56 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.433336542
96.14 0.01 95.70 0.00 93.62 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.60 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2926315417
96.14 0.01 95.70 0.00 93.66 0.04 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.60 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2136114441
96.14 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.63 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3455280245
96.15 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.66 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1806486178
96.15 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.69 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4199929771
96.16 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.72 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.983562759
96.16 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1452230073
96.17 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3843240712
96.17 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2410363030
96.18 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4056144983
96.18 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2978302884
96.18 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.580394285
96.19 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3165406721
96.19 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.2833678395
96.20 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3851233583
96.20 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3790342604
96.21 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.3180636434
96.21 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.1221864102
96.22 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.1595240131
96.22 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 98.15 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.3617213874
96.22 0.01 95.70 0.00 93.66 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.99 0.00 98.18 0.03 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.1742259949
96.23 0.01 95.71 0.01 93.66 0.00 98.31 0.00 92.52 0.00 98.23 0.02 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1579999482
96.23 0.01 95.71 0.00 93.69 0.03 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.856256532
96.24 0.01 95.71 0.00 93.72 0.03 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.795520771
96.24 0.01 95.71 0.00 93.74 0.03 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.969180412
96.24 0.01 95.71 0.00 93.77 0.03 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3025249201
96.25 0.01 95.71 0.00 93.79 0.02 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.228291329
96.25 0.01 95.71 0.00 93.81 0.02 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.3926482766
96.25 0.01 95.71 0.00 93.82 0.01 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2902080723
96.25 0.01 95.71 0.00 93.83 0.01 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3585630774
96.25 0.01 95.71 0.00 93.84 0.01 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.3610630375
96.26 0.01 95.71 0.00 93.85 0.01 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.49674309
96.26 0.01 95.71 0.00 93.86 0.01 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.1772924983
96.26 0.01 95.71 0.00 93.87 0.01 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.2130712332
96.26 0.01 95.71 0.00 93.88 0.01 98.31 0.00 92.52 0.00 98.23 0.00 96.99 0.00 98.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.234800653

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2856331086
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.992865004
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2833910008
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3616131436
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3768774381
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.635460381
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3707413181
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3643482461
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3583630606
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.652252562
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.582129870
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3800306320
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2779433414
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3021202074
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1940713397
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.811011565
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3686848931
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3231346461
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.653861993
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3617054220
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4292872667
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2000935935
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.898215459
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2693540257
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2563270536
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1247271079
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.279818913
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3619350085
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3476169646
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3795927901
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4284579021
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1977554860
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3216227308
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3233299361
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.344784902
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3032106728
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3859900312
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3728836902
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2650425494
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.112411347
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2273144754
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1846758580
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.305688028
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2237627242
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2538627683
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3783288380
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3417311805
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2224270264
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3329226059
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1119784847
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1523835564
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4236627108
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2633856716
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.370498080
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.410840208
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.1658454163
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2865636512
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.755696956
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1841144161
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2912264027
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3875231397
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3175509179
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2510476798
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2991695175
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2252862254
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1199489846
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2427099480
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3492464306
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.588151209
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.252117632
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1875218147
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1893250200
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3972240781
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2495584651
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.832685771
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1024169803
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2059583016
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.4091604962
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Total test records in report: 1257
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.2486649827 Aug 23 10:18:28 AM UTC 24 Aug 23 10:18:57 AM UTC 24 16390900 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.3350386863 Aug 23 10:18:30 AM UTC 24 Aug 23 10:19:02 AM UTC 24 78121500 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.4215812612 Aug 23 10:18:29 AM UTC 24 Aug 23 10:19:59 AM UTC 24 62938100 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.4067499614 Aug 23 10:20:00 AM UTC 24 Aug 23 10:20:25 AM UTC 24 986407500 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.696079173 Aug 23 10:18:34 AM UTC 24 Aug 23 10:20:36 AM UTC 24 124965500 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2418000499 Aug 23 10:18:27 AM UTC 24 Aug 23 10:20:38 AM UTC 24 245844200 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.1030145370 Aug 23 10:18:38 AM UTC 24 Aug 23 10:20:46 AM UTC 24 19436523600 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2358496248 Aug 23 10:18:35 AM UTC 24 Aug 23 10:21:03 AM UTC 24 2926914500 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.1605897277 Aug 23 10:18:58 AM UTC 24 Aug 23 10:21:25 AM UTC 24 42485200 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.1612559986 Aug 23 10:18:37 AM UTC 24 Aug 23 10:21:27 AM UTC 24 136690500 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2267250074 Aug 23 10:21:37 AM UTC 24 Aug 23 10:21:55 AM UTC 24 75314800 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.3050833566 Aug 23 10:21:56 AM UTC 24 Aug 23 10:22:12 AM UTC 24 193715000 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.980891757 Aug 23 10:21:04 AM UTC 24 Aug 23 10:22:25 AM UTC 24 3940245800 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1752541163 Aug 23 10:21:26 AM UTC 24 Aug 23 10:22:35 AM UTC 24 855097000 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2557558010 Aug 23 10:22:26 AM UTC 24 Aug 23 10:22:50 AM UTC 24 88734700 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.3308247925 Aug 23 10:21:57 AM UTC 24 Aug 23 10:23:32 AM UTC 24 567366200 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3528660536 Aug 23 10:19:31 AM UTC 24 Aug 23 10:23:36 AM UTC 24 82920112300 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.3956393745 Aug 23 10:21:28 AM UTC 24 Aug 23 10:23:52 AM UTC 24 2534125700 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.2521826066 Aug 23 10:23:32 AM UTC 24 Aug 23 10:23:57 AM UTC 24 18619900 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2254039376 Aug 23 10:22:36 AM UTC 24 Aug 23 10:24:12 AM UTC 24 593370000 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3980701905 Aug 23 10:23:02 AM UTC 24 Aug 23 10:24:14 AM UTC 24 952590700 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2986761954 Aug 23 10:22:59 AM UTC 24 Aug 23 10:24:16 AM UTC 24 818344300 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.3034342963 Aug 23 10:24:24 AM UTC 24 Aug 23 10:24:40 AM UTC 24 50892100 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.540235031 Aug 23 10:24:25 AM UTC 24 Aug 23 10:24:57 AM UTC 24 64401300 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3021526 Aug 23 10:24:15 AM UTC 24 Aug 23 10:25:14 AM UTC 24 4376120200 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2240609280 Aug 23 10:24:50 AM UTC 24 Aug 23 10:25:15 AM UTC 24 38402700 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.4247874890 Aug 23 10:24:42 AM UTC 24 Aug 23 10:25:17 AM UTC 24 129180900 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.2577954996 Aug 23 10:23:37 AM UTC 24 Aug 23 10:25:32 AM UTC 24 2336889800 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3318614938 Aug 23 10:25:15 AM UTC 24 Aug 23 10:25:33 AM UTC 24 27353900 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.817066798 Aug 23 10:25:18 AM UTC 24 Aug 23 10:25:33 AM UTC 24 22326800 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.473225181 Aug 23 10:25:17 AM UTC 24 Aug 23 10:25:34 AM UTC 24 44484100 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1653172123 Aug 23 10:22:51 AM UTC 24 Aug 23 10:25:40 AM UTC 24 3295017800 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.4143545371 Aug 23 10:25:34 AM UTC 24 Aug 23 10:25:50 AM UTC 24 45084200 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2194679503 Aug 23 10:25:34 AM UTC 24 Aug 23 10:25:50 AM UTC 24 24115400 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.1134585009 Aug 23 10:18:38 AM UTC 24 Aug 23 10:25:51 AM UTC 24 8876131400 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3433369264 Aug 23 10:25:16 AM UTC 24 Aug 23 10:25:51 AM UTC 24 65424600 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2410363030 Aug 23 10:25:35 AM UTC 24 Aug 23 10:25:51 AM UTC 24 45599000 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.1573042214 Aug 23 10:25:22 AM UTC 24 Aug 23 10:25:56 AM UTC 24 311163200 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1846504488 Aug 23 10:25:41 AM UTC 24 Aug 23 10:25:57 AM UTC 24 18643800 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1099058125 Aug 23 10:25:32 AM UTC 24 Aug 23 10:25:58 AM UTC 24 915685100 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.4267884201 Aug 23 10:24:58 AM UTC 24 Aug 23 10:26:03 AM UTC 24 3652135000 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3576080104 Aug 23 10:25:50 AM UTC 24 Aug 23 10:26:06 AM UTC 24 24464600 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.1715955169 Aug 23 10:25:51 AM UTC 24 Aug 23 10:26:07 AM UTC 24 59965600 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1286959286 Aug 23 10:24:17 AM UTC 24 Aug 23 10:26:13 AM UTC 24 5714570700 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.4017585377 Aug 23 10:23:58 AM UTC 24 Aug 23 10:26:18 AM UTC 24 1904542800 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.2205373744 Aug 23 10:23:43 AM UTC 24 Aug 23 10:26:18 AM UTC 24 2901357000 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.1119335981 Aug 23 10:25:51 AM UTC 24 Aug 23 10:26:22 AM UTC 24 27900500 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3006590537 Aug 23 10:25:58 AM UTC 24 Aug 23 10:26:25 AM UTC 24 21768000 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3151900984 Aug 23 10:26:04 AM UTC 24 Aug 23 10:26:35 AM UTC 24 24937600 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3067655209 Aug 23 10:26:07 AM UTC 24 Aug 23 10:26:37 AM UTC 24 65574000 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.4018733912 Aug 23 10:25:51 AM UTC 24 Aug 23 10:26:42 AM UTC 24 102266200 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3994146426 Aug 23 10:23:54 AM UTC 24 Aug 23 10:26:50 AM UTC 24 736246500 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1528017704 Aug 23 10:26:38 AM UTC 24 Aug 23 10:27:02 AM UTC 24 435938500 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.1161127358 Aug 23 10:24:13 AM UTC 24 Aug 23 10:27:29 AM UTC 24 1572957600 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3191564678 Aug 23 10:25:51 AM UTC 24 Aug 23 10:27:30 AM UTC 24 10035192700 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.1408221572 Aug 23 10:25:57 AM UTC 24 Aug 23 10:27:43 AM UTC 24 91248900 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1832930507 Aug 23 10:26:14 AM UTC 24 Aug 23 10:27:44 AM UTC 24 6014642700 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.151085138 Aug 23 10:24:17 AM UTC 24 Aug 23 10:28:12 AM UTC 24 92939938600 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.2078955406 Aug 23 10:26:08 AM UTC 24 Aug 23 10:28:24 AM UTC 24 2826665200 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2294561024 Aug 23 10:27:31 AM UTC 24 Aug 23 10:28:47 AM UTC 24 975160500 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.4023983006 Aug 23 10:27:44 AM UTC 24 Aug 23 10:28:55 AM UTC 24 1884947300 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1898338599 Aug 23 10:26:23 AM UTC 24 Aug 23 10:28:57 AM UTC 24 76384800 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.2121647246 Aug 23 10:28:48 AM UTC 24 Aug 23 10:29:13 AM UTC 24 42275800 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.795520771 Aug 23 10:18:43 AM UTC 24 Aug 23 10:29:48 AM UTC 24 40123178100 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.3832898280 Aug 23 10:28:13 AM UTC 24 Aug 23 10:29:59 AM UTC 24 602557200 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.3993554288 Aug 23 10:29:50 AM UTC 24 Aug 23 10:30:14 AM UTC 24 135743900 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.284773902 Aug 23 10:24:03 AM UTC 24 Aug 23 10:30:14 AM UTC 24 10253118100 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.4055132015 Aug 23 10:29:13 AM UTC 24 Aug 23 10:30:18 AM UTC 24 8650233700 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.4224493311 Aug 23 10:27:45 AM UTC 24 Aug 23 10:30:23 AM UTC 24 2385303100 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3240970199 Aug 23 10:28:56 AM UTC 24 Aug 23 10:30:31 AM UTC 24 715353200 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1800809718 Aug 23 10:29:28 AM UTC 24 Aug 23 10:30:43 AM UTC 24 1758054500 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.3441826486 Aug 23 10:30:31 AM UTC 24 Aug 23 10:31:30 AM UTC 24 7983313200 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3645097304 Aug 23 10:29:59 AM UTC 24 Aug 23 10:31:44 AM UTC 24 2379192900 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.3383639340 Aug 23 10:31:44 AM UTC 24 Aug 23 10:32:01 AM UTC 24 18112200 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.1056021626 Aug 23 10:30:15 AM UTC 24 Aug 23 10:32:06 AM UTC 24 904243400 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.645602144 Aug 23 10:30:24 AM UTC 24 Aug 23 10:32:13 AM UTC 24 937781300 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2830441962 Aug 23 10:31:45 AM UTC 24 Aug 23 10:32:19 AM UTC 24 71645900 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.403398530 Aug 23 10:28:57 AM UTC 24 Aug 23 10:32:21 AM UTC 24 12480105600 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3431574599 Aug 23 10:32:02 AM UTC 24 Aug 23 10:32:34 AM UTC 24 149550300 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2978302884 Aug 23 10:32:14 AM UTC 24 Aug 23 10:32:38 AM UTC 24 39038600 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1846028581 Aug 23 10:32:07 AM UTC 24 Aug 23 10:32:41 AM UTC 24 127944600 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.3563145741 Aug 23 10:30:00 AM UTC 24 Aug 23 10:32:56 AM UTC 24 6531064100 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2132504039 Aug 23 10:32:39 AM UTC 24 Aug 23 10:32:58 AM UTC 24 17098100 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3349911098 Aug 23 10:26:36 AM UTC 24 Aug 23 10:33:13 AM UTC 24 15206008500 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2136114441 Aug 23 10:32:56 AM UTC 24 Aug 23 10:33:13 AM UTC 24 183249700 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2976999247 Aug 23 10:32:58 AM UTC 24 Aug 23 10:33:14 AM UTC 24 22431900 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.721323699 Aug 23 10:32:42 AM UTC 24 Aug 23 10:33:15 AM UTC 24 73095400 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.3054986143 Aug 23 10:32:22 AM UTC 24 Aug 23 10:33:16 AM UTC 24 434112400 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.2602048397 Aug 23 10:26:18 AM UTC 24 Aug 23 10:33:21 AM UTC 24 3722370500 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2838814497 Aug 23 10:33:16 AM UTC 24 Aug 23 10:33:32 AM UTC 24 110733000 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.433336542 Aug 23 10:33:16 AM UTC 24 Aug 23 10:33:32 AM UTC 24 23622100 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3932353248 Aug 23 10:33:17 AM UTC 24 Aug 23 10:33:33 AM UTC 24 37775400 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.2895480604 Aug 23 10:33:14 AM UTC 24 Aug 23 10:33:34 AM UTC 24 725407000 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.786837920 Aug 23 10:30:15 AM UTC 24 Aug 23 10:33:43 AM UTC 24 921853300 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2646676047 Aug 23 10:33:33 AM UTC 24 Aug 23 10:33:48 AM UTC 24 27214400 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2869869472 Aug 23 10:26:09 AM UTC 24 Aug 23 10:33:48 AM UTC 24 3892589100 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.876836959 Aug 23 10:33:33 AM UTC 24 Aug 23 10:33:49 AM UTC 24 151947700 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.356857202 Aug 23 10:33:13 AM UTC 24 Aug 23 10:33:51 AM UTC 24 342319900 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.2550978624 Aug 23 10:33:44 AM UTC 24 Aug 23 10:34:00 AM UTC 24 49899000 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.498083383 Aug 23 10:33:35 AM UTC 24 Aug 23 10:34:06 AM UTC 24 39980900 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.379398261 Aug 23 10:33:49 AM UTC 24 Aug 23 10:34:16 AM UTC 24 16469000 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.124981519 Aug 23 10:33:49 AM UTC 24 Aug 23 10:34:20 AM UTC 24 47905800 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.4204320399 Aug 23 10:31:31 AM UTC 24 Aug 23 10:34:21 AM UTC 24 20216828100 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1287486244 Aug 23 10:20:39 AM UTC 24 Aug 23 10:34:26 AM UTC 24 1984180700 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.610524545 Aug 23 10:30:44 AM UTC 24 Aug 23 10:34:27 AM UTC 24 12188478800 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.1160675972 Aug 23 10:28:25 AM UTC 24 Aug 23 10:34:45 AM UTC 24 7871814600 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1096929081 Aug 23 10:33:34 AM UTC 24 Aug 23 10:35:08 AM UTC 24 10015451500 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.4038873450 Aug 23 10:33:52 AM UTC 24 Aug 23 10:35:31 AM UTC 24 126276600 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.2859323982 Aug 23 10:34:00 AM UTC 24 Aug 23 10:35:53 AM UTC 24 305662300 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3315045127 Aug 23 10:33:47 AM UTC 24 Aug 23 10:35:58 AM UTC 24 45901700 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.4264096012 Aug 23 10:35:32 AM UTC 24 Aug 23 10:35:58 AM UTC 24 1148201000 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2592052871 Aug 23 10:30:19 AM UTC 24 Aug 23 10:36:55 AM UTC 24 13317472200 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3746254650 Aug 23 10:34:28 AM UTC 24 Aug 23 10:36:55 AM UTC 24 378538100 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.2708498054 Aug 23 10:35:09 AM UTC 24 Aug 23 10:36:58 AM UTC 24 4893618500 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.1619069913 Aug 23 10:34:16 AM UTC 24 Aug 23 10:37:16 AM UTC 24 11240738800 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.327815836 Aug 23 10:26:20 AM UTC 24 Aug 23 10:37:30 AM UTC 24 80144323300 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.493821493 Aug 23 10:36:56 AM UTC 24 Aug 23 10:37:55 AM UTC 24 4174931100 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.782500967 Aug 23 10:37:00 AM UTC 24 Aug 23 10:38:12 AM UTC 24 953889200 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.1290306460 Aug 23 10:38:13 AM UTC 24 Aug 23 10:38:38 AM UTC 24 83867400 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.14201869 Aug 23 10:25:15 AM UTC 24 Aug 23 10:38:53 AM UTC 24 169675800 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3014689687 Aug 23 10:37:31 AM UTC 24 Aug 23 10:38:58 AM UTC 24 612950000 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.313499328 Aug 23 10:37:17 AM UTC 24 Aug 23 10:39:00 AM UTC 24 4294625500 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.1657498505 Aug 23 10:38:59 AM UTC 24 Aug 23 10:40:07 AM UTC 24 1675965100 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.1720346337 Aug 23 10:39:00 AM UTC 24 Aug 23 10:40:12 AM UTC 24 955539800 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.747111698 Aug 23 10:38:39 AM UTC 24 Aug 23 10:40:24 AM UTC 24 2670053600 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3497927998 Aug 23 10:25:37 AM UTC 24 Aug 23 10:40:32 AM UTC 24 160782565000 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.4204167538 Aug 23 10:40:08 AM UTC 24 Aug 23 10:40:33 AM UTC 24 93534400 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.3554840051 Aug 23 10:34:20 AM UTC 24 Aug 23 10:41:00 AM UTC 24 2129910200 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3402751864 Aug 23 10:38:53 AM UTC 24 Aug 23 10:41:03 AM UTC 24 2158411700 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.511594845 Aug 23 10:34:06 AM UTC 24 Aug 23 10:41:11 AM UTC 24 457316600 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.3989820292 Aug 23 10:40:13 AM UTC 24 Aug 23 10:41:56 AM UTC 24 1427089100 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.799775616 Aug 23 10:27:04 AM UTC 24 Aug 23 10:42:12 AM UTC 24 328472100 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2400444614 Aug 23 10:41:12 AM UTC 24 Aug 23 10:42:22 AM UTC 24 23817169700 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.3665627232 Aug 23 10:42:23 AM UTC 24 Aug 23 10:42:38 AM UTC 24 131468200 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.2287935471 Aug 23 10:40:34 AM UTC 24 Aug 23 10:43:07 AM UTC 24 1553513900 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.2518445606 Aug 23 10:40:33 AM UTC 24 Aug 23 10:43:27 AM UTC 24 1776189700 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.4197061220 Aug 23 10:40:25 AM UTC 24 Aug 23 10:43:33 AM UTC 24 1699415100 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2738037225 Aug 23 10:41:04 AM UTC 24 Aug 23 10:43:47 AM UTC 24 1413121700 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.1417095547 Aug 23 10:43:13 AM UTC 24 Aug 23 10:43:49 AM UTC 24 124193700 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.790124310 Aug 23 10:43:28 AM UTC 24 Aug 23 10:43:52 AM UTC 24 111463300 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.97168675 Aug 23 10:43:50 AM UTC 24 Aug 23 10:44:06 AM UTC 24 81204300 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2715256630 Aug 23 10:44:06 AM UTC 24 Aug 23 10:44:23 AM UTC 24 164398700 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3806589261 Aug 23 10:43:53 AM UTC 24 Aug 23 10:44:28 AM UTC 24 113913400 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1573539207 Aug 23 10:37:56 AM UTC 24 Aug 23 10:44:28 AM UTC 24 7954918500 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.3714317260 Aug 23 10:44:23 AM UTC 24 Aug 23 10:44:39 AM UTC 24 39935700 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.2130712332 Aug 23 10:44:29 AM UTC 24 Aug 23 10:44:48 AM UTC 24 677881500 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.3300596393 Aug 23 10:43:41 AM UTC 24 Aug 23 10:44:49 AM UTC 24 8754453400 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.1903829199 Aug 23 10:44:39 AM UTC 24 Aug 23 10:44:56 AM UTC 24 15309100 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.13610981 Aug 23 10:18:40 AM UTC 24 Aug 23 10:45:00 AM UTC 24 125143478700 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2533927963 Aug 23 10:44:28 AM UTC 24 Aug 23 10:45:04 AM UTC 24 624030900 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.1649669404 Aug 23 10:44:48 AM UTC 24 Aug 23 10:45:04 AM UTC 24 14812500 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.1425197203 Aug 23 10:44:50 AM UTC 24 Aug 23 10:45:05 AM UTC 24 52779000 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3912003533 Aug 23 10:45:01 AM UTC 24 Aug 23 10:45:16 AM UTC 24 15453800 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.585879710 Aug 23 10:45:05 AM UTC 24 Aug 23 10:45:20 AM UTC 24 15027000 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.958669691 Aug 23 10:42:12 AM UTC 24 Aug 23 10:45:33 AM UTC 24 76024114100 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.1137554760 Aug 23 10:45:17 AM UTC 24 Aug 23 10:45:33 AM UTC 24 38705900 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1817652686 Aug 23 10:33:22 AM UTC 24 Aug 23 10:45:34 AM UTC 24 95257399000 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2321620466 Aug 23 10:45:06 AM UTC 24 Aug 23 10:45:39 AM UTC 24 52723000 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.294159004 Aug 23 10:34:27 AM UTC 24 Aug 23 10:45:46 AM UTC 24 160175967400 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.534048183 Aug 23 10:41:56 AM UTC 24 Aug 23 10:45:47 AM UTC 24 24935445500 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.3605236513 Aug 23 10:45:33 AM UTC 24 Aug 23 10:46:03 AM UTC 24 18710300 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.1613280193 Aug 23 10:45:35 AM UTC 24 Aug 23 10:46:06 AM UTC 24 36696900 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.2325000027 Aug 23 10:45:40 AM UTC 24 Aug 23 10:46:46 AM UTC 24 70903300 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3483788835 Aug 23 10:45:05 AM UTC 24 Aug 23 10:46:47 AM UTC 24 10012043400 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1131440574 Aug 23 10:45:21 AM UTC 24 Aug 23 10:47:07 AM UTC 24 2697187400 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.969180412 Aug 23 10:45:47 AM UTC 24 Aug 23 10:47:37 AM UTC 24 148156000 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.4095838318 Aug 23 10:45:47 AM UTC 24 Aug 23 10:47:50 AM UTC 24 128556600 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3878294386 Aug 23 10:46:04 AM UTC 24 Aug 23 10:48:12 AM UTC 24 15637489900 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.341914351 Aug 23 10:45:34 AM UTC 24 Aug 23 10:48:13 AM UTC 24 5180065400 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.234800653 Aug 23 10:47:51 AM UTC 24 Aug 23 10:48:17 AM UTC 24 585718800 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3552425146 Aug 23 10:41:01 AM UTC 24 Aug 23 10:48:29 AM UTC 24 16781384400 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1214390400 Aug 23 10:33:49 AM UTC 24 Aug 23 10:48:34 AM UTC 24 3284618500 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.1020583400 Aug 23 10:46:48 AM UTC 24 Aug 23 10:48:50 AM UTC 24 35604400 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.1409877433 Aug 23 10:48:34 AM UTC 24 Aug 23 10:49:42 AM UTC 24 6512309300 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.1187478843 Aug 23 10:48:51 AM UTC 24 Aug 23 10:50:05 AM UTC 24 1846043300 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.1690114407 Aug 23 10:35:59 AM UTC 24 Aug 23 10:50:30 AM UTC 24 3630446300 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2705706761 Aug 23 10:50:06 AM UTC 24 Aug 23 10:51:24 AM UTC 24 1000344200 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.2222118405 Aug 23 10:49:43 AM UTC 24 Aug 23 10:51:48 AM UTC 24 2379738600 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.3644949943 Aug 23 10:51:24 AM UTC 24 Aug 23 10:51:49 AM UTC 24 65999800 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.3634203810 Aug 23 10:46:06 AM UTC 24 Aug 23 10:52:15 AM UTC 24 2956670500 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.949156795 Aug 23 10:19:02 AM UTC 24 Aug 23 10:53:02 AM UTC 24 537427402700 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.1657169533 Aug 23 10:52:16 AM UTC 24 Aug 23 10:53:10 AM UTC 24 701640600 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2196448808 Aug 23 10:51:48 AM UTC 24 Aug 23 10:53:24 AM UTC 24 1920440800 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3066298142 Aug 23 10:53:11 AM UTC 24 Aug 23 10:53:36 AM UTC 24 41553400 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4056144983 Aug 23 10:20:26 AM UTC 24 Aug 23 10:54:07 AM UTC 24 158302451900 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1267757184 Aug 23 10:53:03 AM UTC 24 Aug 23 10:54:27 AM UTC 24 3831288100 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.782707853 Aug 23 10:51:50 AM UTC 24 Aug 23 10:54:31 AM UTC 24 3263489300 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2503835369 Aug 23 10:26:19 AM UTC 24 Aug 23 10:54:51 AM UTC 24 397582814700 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.2312805626 Aug 23 10:53:25 AM UTC 24 Aug 23 10:55:16 AM UTC 24 845800200 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.51079014 Aug 23 10:25:59 AM UTC 24 Aug 23 10:55:36 AM UTC 24 2844422800 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.2441974253 Aug 23 10:53:37 AM UTC 24 Aug 23 10:55:56 AM UTC 24 1212786900 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.2618656063 Aug 23 10:55:17 AM UTC 24 Aug 23 10:56:21 AM UTC 24 6688562700 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.835009042 Aug 23 10:26:25 AM UTC 24 Aug 23 10:56:36 AM UTC 24 575999686800 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.715391937 Aug 23 10:56:21 AM UTC 24 Aug 23 10:56:38 AM UTC 24 23201300 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.2666964669 Aug 23 10:54:28 AM UTC 24 Aug 23 10:56:52 AM UTC 24 6047293800 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.2223099216 Aug 23 10:54:52 AM UTC 24 Aug 23 10:56:57 AM UTC 24 3072073200 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.1639180190 Aug 23 10:50:31 AM UTC 24 Aug 23 10:56:59 AM UTC 24 11433554000 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.4273691740 Aug 23 10:56:36 AM UTC 24 Aug 23 10:57:10 AM UTC 24 117619900 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2949385558 Aug 23 10:56:38 AM UTC 24 Aug 23 10:57:10 AM UTC 24 28536600 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.3202192135 Aug 23 10:54:12 AM UTC 24 Aug 23 10:57:12 AM UTC 24 3480388100 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2060362997 Aug 23 10:44:57 AM UTC 24 Aug 23 10:57:21 AM UTC 24 41795960700 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3510721200 Aug 23 10:56:59 AM UTC 24 Aug 23 10:57:22 AM UTC 24 27080200 ps
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T360 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.365778370 Aug 23 10:57:13 AM UTC 24 Aug 23 10:57:31 AM UTC 24 16036000 ps
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T273 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.212408297 Aug 23 10:57:48 AM UTC 24 Aug 23 10:58:04 AM UTC 24 39232100 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.360419317 Aug 23 10:57:50 AM UTC 24 Aug 23 10:58:06 AM UTC 24 15651600 ps
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T458 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1102584248 Aug 23 10:59:27 AM UTC 24 Aug 23 10:59:53 AM UTC 24 1474168100 ps
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T161 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1008857270 Aug 23 11:01:45 AM UTC 24 Aug 23 11:02:56 AM UTC 24 4714434200 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.1400624901 Aug 23 10:32:35 AM UTC 24 Aug 23 11:03:07 AM UTC 24 2714260100 ps
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T465 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.3235599440 Aug 23 11:03:13 AM UTC 24 Aug 23 11:04:16 AM UTC 24 2125074200 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1884069589 Aug 23 10:58:15 AM UTC 24 Aug 23 11:04:20 AM UTC 24 66718500 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.327195550 Aug 23 11:02:00 AM UTC 24 Aug 23 11:04:21 AM UTC 24 3765111200 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.2421389851 Aug 23 11:02:57 AM UTC 24 Aug 23 11:04:36 AM UTC 24 1163196500 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.3584271438 Aug 23 11:04:17 AM UTC 24 Aug 23 11:04:42 AM UTC 24 27995200 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.306001922 Aug 23 11:03:12 AM UTC 24 Aug 23 11:04:55 AM UTC 24 1276371900 ps
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T470 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.3969240505 Aug 23 11:04:21 AM UTC 24 Aug 23 11:06:32 AM UTC 24 2387666700 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1230493350 Aug 23 10:48:17 AM UTC 24 Aug 23 11:06:47 AM UTC 24 14661999000 ps
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T472 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.1326504515 Aug 23 11:04:43 AM UTC 24 Aug 23 11:07:31 AM UTC 24 5842692800 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.3240278372 Aug 23 11:04:22 AM UTC 24 Aug 23 11:07:34 AM UTC 24 30350633900 ps
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