Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	265343	1		T1	1		T2	2		T3	2
all_values[1]	265343	1		T1	1		T2	2		T3	2
all_values[2]	265343	1		T1	1		T2	2		T3	2
all_values[3]	265343	1		T1	1		T2	2		T3	2
all_values[4]	265343	1		T1	1		T2	2		T3	2
all_values[5]	265343	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	537098	1		T1	6		T2	12		T3	12
auto[1]	1054960	1		T26	6472		T38	55932		T30	6260

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	779498	1		T1	4		T2	7		T3	7
auto[1]	812560	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	265187	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	156	1		T240	7		T241	5		T249	3
all_values[1]	auto[0]	auto[1]	265179	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	164	1		T240	6		T241	4		T249	1
all_values[2]	auto[0]	auto[0]	1621	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	76	1		T240	2		T241	1		T318	5
all_values[2]	auto[1]	auto[0]	263600	1		T26	1618		T38	13983		T30	1565
all_values[2]	auto[1]	auto[1]	46	1		T241	1		T249	1		T318	1
all_values[3]	auto[0]	auto[0]	1631	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	60	1		T241	1		T318	2		T319	2
all_values[3]	auto[1]	auto[0]	83139	1		T26	1618		T38	14		T30	1565
all_values[3]	auto[1]	auto[1]	180513	1		T38	13969		T39	1203		T40	6560
all_values[4]	auto[0]	auto[0]	1118	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	544	1		T2	1		T3	1		T13	1
all_values[4]	auto[1]	auto[0]	163213	1		T26	1		T38	12275		T30	1
all_values[4]	auto[1]	auto[1]	100468	1		T26	1617		T38	1708		T30	1564
all_values[5]	auto[0]	auto[0]	1583	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	99	1		T41	1		T42	1		T43	1
all_values[5]	auto[1]	auto[0]	263593	1		T26	1618		T38	13983		T30	1565
all_values[5]	auto[1]	auto[1]	68	1		T240	2		T241	1		T249	1