Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	238596	1		T2	4		T3	7		T13	30
auto[FlashEraseBank]	264240	1		T13	6		T14	2		T18	2

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	249328	1		T2	2		T3	5		T13	36
auto[FlashOpProgram]	234139	1		T2	1		T3	2		T14	9
auto[FlashOpErase]	15369	1		T2	1		T19	357		T20	4
auto[FlashOpInvalid]	4000	1		T48	200		T134	200		T147	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	249328	1		T2	2		T3	5		T13	36
op[FlashOpProgram]	234139	1		T2	1		T3	2		T14	9
op[FlashOpErase]	15369	1		T2	1		T19	357		T20	4
read_erase_read	533	1		T20	2		T32	4		T27	15
read_prog_read	784	1		T3	2		T14	8		T20	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	363399	1		T2	4		T3	2		T13	36
auto[FlashPartInfo]	135727	1		T3	1		T19	1427		T48	12
auto[FlashPartInfo1]	849	1		T3	3		T32	1		T41	1
auto[FlashPartInfo2]	2861	1		T3	1		T52	6		T32	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	180151	1		T2	2		T3	2		T13	36
auto[FlashPartData]	auto[FlashOpProgram]	175762	1		T2	1		T14	9		T18	2
auto[FlashPartData]	auto[FlashOpErase]	3576	1		T2	1		T20	4		T15	2
auto[FlashPartData]	auto[FlashOpInvalid]	3910	1		T48	196		T134	194		T147	196
auto[FlashPartInfo]	auto[FlashOpRead]	66642	1		T19	713		T48	4		T52	241
auto[FlashPartInfo]	auto[FlashOpProgram]	57246	1		T3	1		T19	357		T48	2
auto[FlashPartInfo]	auto[FlashOpErase]	11759	1		T19	357		T48	2		T32	22
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T48	4		T134	2		T147	2
auto[FlashPartInfo1]	auto[FlashOpRead]	675	1		T3	3		T41	1		T63	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T32	1		T134	2		T152	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T134	2		T397	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T134	4		T397	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1860	1		T52	6		T32	1		T41	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	966	1		T3	1		T71	10		T42	1
auto[FlashPartInfo2]	auto[FlashOpErase]	31	1		T27	2		T147	1		T153	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T147	2		T398	2		-	-