Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30425	1		T2	4		T14	36		T19	712
auto[1]	44	1		T27	8		T91	4		T145	3
auto[2]	65	1		T27	1		T160	4		T149	2
auto[3]	228	1		T27	1		T28	1		T29	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7706	1		T2	1		T14	9		T19	178
evic_idx[1]	7685	1		T2	1		T14	9		T19	178
evic_idx[2]	7696	1		T2	1		T14	9		T19	178
evic_idx[3]	7675	1		T2	1		T14	9		T19	178

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29770	1		T2	4		T19	712		T20	12
evic_op[2]	323	1		T14	36		T20	16		T15	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7382	1		T2	1		T19	178		T20	3
evic_idx[0]	evic_op[1]	auto[1]	10	1		T27	3		T145	1		T399	4
evic_idx[0]	evic_op[1]	auto[2]	11	1		T27	1		T149	1		T400	1
evic_idx[0]	evic_op[1]	auto[3]	54	1		T149	1		T401	6		T402	4
evic_idx[0]	evic_op[2]	auto[0]	60	1		T14	9		T20	4		T57	1
evic_idx[0]	evic_op[2]	auto[1]	5	1		T91	1		T92	1		T316	1
evic_idx[0]	evic_op[2]	auto[2]	4	1		T403	1		T129	1		T404	2
evic_idx[0]	evic_op[2]	auto[3]	12	1		T215	1		T405	1		T406	1
evic_idx[1]	evic_op[1]	auto[0]	7378	1		T2	1		T19	178		T20	3
evic_idx[1]	evic_op[1]	auto[1]	5	1		T27	1		T145	1		T399	2
evic_idx[1]	evic_op[1]	auto[2]	8	1		T400	1		T407	2		T408	1
evic_idx[1]	evic_op[1]	auto[3]	48	1		T401	5		T402	5		T409	3
evic_idx[1]	evic_op[2]	auto[0]	61	1		T14	9		T20	4		T57	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T91	1		T92	1		T316	1
evic_idx[1]	evic_op[2]	auto[2]	5	1		T403	1		T410	2		T411	1
evic_idx[1]	evic_op[2]	auto[3]	10	1		T412	1		T403	1		T413	1
evic_idx[2]	evic_op[1]	auto[0]	7384	1		T2	1		T19	178		T20	3
evic_idx[2]	evic_op[1]	auto[1]	4	1		T27	2		T399	1		T414	1
evic_idx[2]	evic_op[1]	auto[2]	7	1		T149	1		T400	1		T407	1
evic_idx[2]	evic_op[1]	auto[3]	48	1		T27	1		T145	1		T401	5
evic_idx[2]	evic_op[2]	auto[0]	63	1		T14	9		T20	4		T15	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T91	1		T316	2		-	-
evic_idx[2]	evic_op[2]	auto[2]	5	1		T45	1		T403	1		T129	1
evic_idx[2]	evic_op[2]	auto[3]	15	1		T28	1		T29	1		T415	1
evic_idx[3]	evic_op[1]	auto[0]	7381	1		T2	1		T19	178		T20	3
evic_idx[3]	evic_op[1]	auto[1]	6	1		T27	2		T145	1		T399	2
evic_idx[3]	evic_op[1]	auto[2]	5	1		T400	1		T407	1		T414	3
evic_idx[3]	evic_op[1]	auto[3]	39	1		T401	6		T402	4		T409	1
evic_idx[3]	evic_op[2]	auto[0]	63	1		T14	9		T20	4		T57	1
evic_idx[3]	evic_op[2]	auto[1]	8	1		T91	1		T92	1		T316	2
evic_idx[3]	evic_op[2]	auto[2]	4	1		T403	1		T410	1		T416	1
evic_idx[3]	evic_op[2]	auto[3]	2	1		T417	1		T410	1		-	-