Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	7784	1		T38	1559		T321	1307		T322	2563
rd_lvl[2]	14796	1		T38	2309		T323	1465		T321	2226
rd_lvl[3]	13063	1		T38	981		T323	612		T321	908
rd_lvl[4]	29344	1		T38	1721		T39	745		T40	6560
rd_lvl[5]	14837	1		T38	801		T39	190		T324	1498
rd_lvl[6]	22118	1		T38	852		T39	15		T324	847
rd_lvl[7]	10466	1		T38	689		T39	102		T324	333
rd_lvl[8]	11000	1		T38	940		T39	21		T324	1179
rd_lvl[9]	7893	1		T38	1390		T321	1047		T325	649
rd_lvl[10]	8435	1		T38	502		T321	357		T326	1308
rd_lvl[11]	6945	1		T38	1595		T321	1805		T326	364
rd_lvl[12]	8987	1		T39	93		T327	1422		T323	133
rd_lvl[13]	3461	1		T327	231		T323	133		T328	581
rd_lvl[14]	7534	1		T35	281		T328	1109		T36	96
rd_lvl[15]	4196	1		T35	1443		T36	1		T37	11