Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	265343	1		T1	1		T2	2		T3	2
all_pins[1]	265343	1		T1	1		T2	2		T3	2
all_pins[2]	265343	1		T1	1		T2	2		T3	2
all_pins[3]	265343	1		T1	1		T2	2		T3	2
all_pins[4]	265343	1		T1	1		T2	2		T3	2
all_pins[5]	265343	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1307646	1		T1	6		T2	12		T3	12
values[0x1]	284412	1		T26	1617		T38	15075		T30	1564
transitions[0x0=>0x1]	257568	1		T26	1617		T38	13353		T30	1564
transitions[0x1=>0x0]	257557	1		T26	1617		T38	13353		T30	1564

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	265187	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	156	1		T240	7		T241	5		T249	3
all_pins[0]	transitions[0x0=>0x1]	73	1		T240	2		T241	2		T249	2
all_pins[0]	transitions[0x1=>0x0]	81	1		T240	1		T241	1		T318	1
all_pins[1]	values[0x0]	265179	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	164	1		T240	6		T241	4		T249	1
all_pins[1]	transitions[0x0=>0x1]	142	1		T240	6		T241	4		T318	6
all_pins[1]	transitions[0x1=>0x0]	2938	1		T332	188		T333	1206		T334	172
all_pins[2]	values[0x0]	262383	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	2960	1		T332	188		T333	1206		T334	172
all_pins[2]	transitions[0x0=>0x1]	34	1		T241	1		T249	1		T319	1
all_pins[2]	transitions[0x1=>0x0]	171030	1		T38	13339		T39	1166		T40	6560
all_pins[3]	values[0x0]	91387	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	173956	1		T38	13339		T39	1166		T40	6560
all_pins[3]	transitions[0x0=>0x1]	150206	1		T38	11617		T39	825		T40	4920
all_pins[3]	transitions[0x1=>0x0]	83358	1		T26	1617		T38	14		T30	1564
all_pins[4]	values[0x0]	158235	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	107108	1		T26	1617		T38	1736		T30	1564
all_pins[4]	transitions[0x0=>0x1]	107091	1		T26	1617		T38	1736		T30	1564
all_pins[4]	transitions[0x1=>0x0]	51	1		T240	1		T241	1		T249	1
all_pins[5]	values[0x0]	265275	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	68	1		T240	2		T241	1		T249	1
all_pins[5]	transitions[0x0=>0x1]	22	1		T249	1		T319	1		T335	1
all_pins[5]	transitions[0x1=>0x0]	99	1		T240	4		T241	4		T249	2