Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T240	7		T241	7		T249	4
all_values[1]	281	1		T240	7		T241	7		T249	4
all_values[2]	281	1		T240	7		T241	7		T249	4
all_values[3]	281	1		T240	7		T241	7		T249	4
all_values[4]	281	1		T240	7		T241	7		T249	4
all_values[5]	281	1		T240	7		T241	7		T249	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	951	1		T240	20		T241	27		T249	10
auto[1]	735	1		T240	22		T241	15		T249	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	524	1		T240	14		T241	19		T249	12
auto[1]	1162	1		T240	28		T241	23		T249	12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	983	1		T240	27		T241	28		T249	19
auto[1]	703	1		T240	15		T241	14		T249	5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	93	1		T241	3		T318	1		T319	4
all_values[0]	auto[0]	auto[1]	auto[1]	72	1		T240	4		T241	2		T249	2
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T240	1		T241	1		T249	1
all_values[0]	auto[1]	auto[1]	auto[1]	60	1		T240	2		T241	1		T249	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1		T240	2		T249	2		T318	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1		T240	4		T241	2		T249	2
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T240	1		T241	4		T318	1
all_values[1]	auto[1]	auto[1]	auto[1]	44	1		T241	1		T318	1		T319	3
all_values[2]	auto[0]	auto[0]	auto[0]	93	1		T240	2		T241	3		T249	2
all_values[2]	auto[0]	auto[1]	auto[0]	66	1		T240	3		T241	2		T249	1
all_values[2]	auto[1]	auto[0]	auto[1]	77	1		T240	1		T241	2		T318	5
all_values[2]	auto[1]	auto[1]	auto[1]	45	1		T240	1		T249	1		T318	1
all_values[3]	auto[0]	auto[0]	auto[0]	98	1		T240	2		T241	4		T249	2
all_values[3]	auto[0]	auto[1]	auto[0]	75	1		T240	4		T241	2		T249	2
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T241	1		T318	1		T319	1
all_values[3]	auto[1]	auto[1]	auto[1]	48	1		T240	1		T318	2		T319	3
all_values[4]	auto[0]	auto[0]	auto[0]	50	1		T240	2		T241	3		T249	1
all_values[4]	auto[0]	auto[0]	auto[1]	32	1		T240	1		T241	1		T318	1
all_values[4]	auto[0]	auto[1]	auto[0]	41	1		T240	1		T241	2		T249	3
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T318	2		T319	3		T320	2
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T240	2		T241	1		T318	1
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T240	1		T318	1		T319	2
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T241	1		T249	1		T318	2
all_values[5]	auto[0]	auto[0]	auto[1]	29	1		T240	1		T241	1		T318	1
all_values[5]	auto[0]	auto[1]	auto[0]	46	1		T241	2		T318	2		T319	2
all_values[5]	auto[0]	auto[1]	auto[1]	31	1		T240	1		T249	1		T319	1
all_values[5]	auto[1]	auto[0]	auto[1]	80	1		T240	5		T241	2		T249	1
all_values[5]	auto[1]	auto[1]	auto[1]	40	1		T241	1		T249	1		T318	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal