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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A	0	0	332875393	14606656	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A	0	0	332875393	14606656	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A	0	0	332875310	14606655	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	332875393	302795342	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	332875393	14606656	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	332875393	14606656	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A	0	0	332875393	29213317	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M	0	0	332791349	14606603	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A	0	0	332875393	14606656	0	0
tb.dut.u_flash_hw_if.DisableChk_A	0	0	317850766	5095704	0	44
tb.dut.u_flash_hw_if.ProgRdVerify_A	0	0	316194642	1845785	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq	0	0	332875515	9710	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq	0	0	332779908	9379	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq	0	0	332875515	9675	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq	0	0	321937685	9372	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A	0	0	1026	1026	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs_A	0	0	332875515	332008781	0	0
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A	0	0	1026	1026	0	0
tb.dut.u_flash_hw_if.u_state_regs_A	0	0	332875515	332008781	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	326170423	325303689	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	326170423	325269459	0	2673
tb.dut.u_flash_mp.BankEraseData_A	0	0	332875515	4589179	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	332875515	10814100	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	332875515	211564851	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	332875515	239564477	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	332875515	27999626	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	327876923	126196	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	332875515	15403279	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	332875515	126697777	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	332875515	239438221	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	332875515	239438221	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	1026	1026	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	1026	1026	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	1026	1026	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	1026	1026	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	1026	1026	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	1026	1026	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	326145975	325279241	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	326145975	325245161	0	2523
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	326170423	325303689	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	326170423	325269459	0	2673
tb.dut.u_prog_fifo.DataKnown_A	0	0	332875393	141584421	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	141584421	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	326170301	325303567	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	326170301	325303567	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	1026	1026	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	332875393	332008659	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1026	1026	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1026	1026	0	0
tb.dut.u_reg_core.en2addrHit	0	0	335615710	24980600	0	0
tb.dut.u_reg_core.reAfterRv	0	0	335615710	24980585	0	0
tb.dut.u_reg_core.rePulse	0	0	335615710	22428804	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	335615710	334661758	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	335615710	334661758	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	335615588	31630189	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	335615588	41285688	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	335615588	2170333	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	335615588	3522874	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	335615588	4037284	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	335615588	5113516	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	335615588	25360799	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	335615588	32649298	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	335615588	334661636	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1241	1241	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1241	1241	0	0
tb.dut.u_reg_core.wePulse	0	0	335615710	2551781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	332875515	332008781	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	326170423	325303689	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	326170423	325269459	0	2673
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	326170423	325303689	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	326170423	325269459	0	2673
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	326170423	325303689	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	326170423	325269459	0	2673
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	326170423	325303689	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	326170423	325269459	0	2673
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	332875393	48486949	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	48486949	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnownIfFifoKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.TlOutValidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DataKnown_A	0	0	332875393	32523021	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	32523021	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	332875393	4121759	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	332875393	4121759	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	332875393	34269055	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	34269055	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	332875393	5862421	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	5862421	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.SramReadbackAndIntg	0	0	1026	1026	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	332875393	32523021	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	32523021	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1026	1026	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	326170301	325303567	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	326170301	325303567	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1026	1026	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	332875393	332008659	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1026	1026	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.TlOutValidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	332875393	3492786	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	3492786	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1026	1026	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.TlOutValidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	332875393	3370386	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	332232491	3364092	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	332875393	5108348	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	5108348	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	332666161	5100689	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	5111159	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1026	1026	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	332875393	3370386	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	332875393	332008659	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	332875393	3370386	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	332875393	0	0	1021
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	332875393	0	0	1021
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	326170301	325269352	0	2673
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	332875393	0	0	1021
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	332875393	0	0	1021
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	332875393	0	0	1021
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	332875393	0	0	1021
tb.dut.u_flash_hw_if.DisableChk_A	0	0	317850766	5095704	0	44

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