Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo.u_sram_byte	100.00	100.00					100.00
tb.dut.u_to_rd_fifo.u_sram_byte	100.00	100.00					100.00
tb.dut.u_tl_adapter_eflash.u_sram_byte	100.00	100.00					100.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.34	92.65	64.66			71.43	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.86	95.83	73.39			86.21	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.24	97.18	78.12			89.66	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	710	0	0
CONT_ASSIGN	716	0	0
CONT_ASSIGN	717	0	0

701                         // In this case we pass everything just through.
702        1/1              assign tl_sram_o = tl_i;
           Tests:       T1 T2 T3 
703        1/1              assign tl_o = tl_sram_i;
           Tests:       T1 T2 T3 
704        1/1              assign error_o = error_i;
           Tests:       T1 T2 T3 
705                         assign alert_o = 1'b0;
706                         assign compound_txn_in_progress_o = 1'b0;
707                     
708                         // Signal only used in readback mode.
709                         mubi4_t unused_readback_en;
710        unreachable      assign unused_readback_en = readback_en_i;
711                     
712                       end
713                     
714                       // Signals only used for SVA.
715                       logic unused_write_pending, unused_wr_collision;
716        unreachable    assign unused_write_pending = write_pending_i;
717        unreachable    assign unused_wr_collision = wr_collision_i;

---

Assert Coverage for Module : tlul_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	3078	3078	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	3078	3078	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T8	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	710	0	0
CONT_ASSIGN	716	0	0
CONT_ASSIGN	717	0	0

701                         // In this case we pass everything just through.
702        1/1              assign tl_sram_o = tl_i;
           Tests:       T1 T2 T3 
703        1/1              assign tl_o = tl_sram_i;
           Tests:       T1 T2 T3 
704        1/1              assign error_o = error_i;
           Tests:       T1 T2 T15 
705                         assign alert_o = 1'b0;
706                         assign compound_txn_in_progress_o = 1'b0;
707                     
708                         // Signal only used in readback mode.
709                         mubi4_t unused_readback_en;
710        unreachable      assign unused_readback_en = readback_en_i;
711                     
712                       end
713                     
714                       // Signals only used for SVA.
715                       logic unused_write_pending, unused_wr_collision;
716        unreachable    assign unused_write_pending = write_pending_i;
717        unreachable    assign unused_wr_collision = wr_collision_i;

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1026	1026	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	710	0	0
CONT_ASSIGN	716	0	0
CONT_ASSIGN	717	0	0

701                         // In this case we pass everything just through.
702        1/1              assign tl_sram_o = tl_i;
           Tests:       T1 T2 T3 
703        1/1              assign tl_o = tl_sram_i;
           Tests:       T1 T2 T3 
704        1/1              assign error_o = error_i;
           Tests:       T1 T3 T15 
705                         assign alert_o = 1'b0;
706                         assign compound_txn_in_progress_o = 1'b0;
707                     
708                         // Signal only used in readback mode.
709                         mubi4_t unused_readback_en;
710        unreachable      assign unused_readback_en = readback_en_i;
711                     
712                       end
713                     
714                       // Signals only used for SVA.
715                       logic unused_write_pending, unused_wr_collision;
716        unreachable    assign unused_write_pending = write_pending_i;
717        unreachable    assign unused_wr_collision = wr_collision_i;

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1026	1026	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	710	0	0
CONT_ASSIGN	716	0	0
CONT_ASSIGN	717	0	0

701                         // In this case we pass everything just through.
702        1/1              assign tl_sram_o = tl_i;
           Tests:       T1 T2 T3 
703        1/1              assign tl_o = tl_sram_i;
           Tests:       T1 T2 T3 
704        1/1              assign error_o = error_i;
           Tests:       T1 T2 T4 
705                         assign alert_o = 1'b0;
706                         assign compound_txn_in_progress_o = 1'b0;
707                     
708                         // Signal only used in readback mode.
709                         mubi4_t unused_readback_en;
710        unreachable      assign unused_readback_en = readback_en_i;
711                     
712                       end
713                     
714                       // Signals only used for SVA.
715                       logic unused_write_pending, unused_wr_collision;
716        unreachable    assign unused_write_pending = write_pending_i;
717        unreachable    assign unused_wr_collision = wr_collision_i;

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	1026	1026	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0