Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 19793 1 T136 694 T140 463 T137 294
full_word 3811392 1 T8 454 T6 16 T20 10


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3830902 1 T8 454 T6 16 T20 10
auto[TlIntgErrCmd] 81 1 T264 3 T265 2 T266 1
auto[TlIntgErrData] 121 1 T264 2 T265 4 T266 5
auto[TlIntgErrBoth] 81 1 T264 5 T265 3 T266 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3803862 1 T8 454 T6 16 T20 10
auto[1] 27323 1 T136 830 T140 529 T137 384


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrCmd]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1128 1 T136 55 T140 27 T137 21
auto[TlIntgErrNone] partial auto[1] 18405 1 T136 639 T140 436 T137 273
auto[TlIntgErrNone] full_word auto[0] 3802618 1 T8 454 T6 16 T20 10
auto[TlIntgErrNone] full_word auto[1] 8751 1 T136 191 T140 93 T137 111
auto[TlIntgErrCmd] partial auto[0] 29 1 T264 1 T265 1 T376 3
auto[TlIntgErrCmd] partial auto[1] 47 1 T264 2 T265 1 T266 1
auto[TlIntgErrCmd] full_word auto[1] 5 1 T371 1 T372 2 T381 1
auto[TlIntgErrData] partial auto[0] 51 1 T264 1 T265 3 T266 2
auto[TlIntgErrData] partial auto[1] 55 1 T265 1 T266 3 T376 1
auto[TlIntgErrData] full_word auto[0] 3 1 T264 1 T374 1 T375 1
auto[TlIntgErrData] full_word auto[1] 12 1 T374 1 T371 2 T382 1
auto[TlIntgErrBoth] partial auto[0] 32 1 T264 2 T265 1 T266 1
auto[TlIntgErrBoth] partial auto[1] 46 1 T264 3 T265 2 T266 2
auto[TlIntgErrBoth] full_word auto[0] 1 1 T375 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 2 1 T372 1 T373 1 - -


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 22539753 1 T1 63 T2 1141 T3 356
full_word 7820816 1 T1 49 T2 157 T3 243


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 30360259 1 T1 112 T2 1298 T3 599
auto[TlIntgErrCmd] 108 1 T264 2 T265 3 T266 3
auto[TlIntgErrData] 103 1 T264 1 T265 5 T266 4
auto[TlIntgErrBoth] 99 1 T264 7 T265 2 T266 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25796750 1 T1 61 T2 1132 T3 493
auto[1] 4563819 1 T1 51 T2 166 T3 106


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 21803311 1 T1 60 T2 1127 T3 335
auto[TlIntgErrNone] partial auto[1] 736162 1 T1 3 T2 14 T3 21
auto[TlIntgErrNone] full_word auto[0] 3993295 1 T1 1 T2 5 T3 158
auto[TlIntgErrNone] full_word auto[1] 3827491 1 T1 48 T2 152 T3 85
auto[TlIntgErrCmd] partial auto[0] 45 1 T264 1 T265 2 T376 1
auto[TlIntgErrCmd] partial auto[1] 51 1 T264 1 T265 1 T266 2
auto[TlIntgErrCmd] full_word auto[0] 5 1 T374 1 T378 1 T383 1
auto[TlIntgErrCmd] full_word auto[1] 7 1 T266 1 T384 1 T377 1
auto[TlIntgErrData] partial auto[0] 49 1 T265 2 T266 3 T385 1
auto[TlIntgErrData] partial auto[1] 42 1 T264 1 T265 3 T376 4
auto[TlIntgErrData] full_word auto[0] 7 1 T374 1 T372 1 T377 1
auto[TlIntgErrData] full_word auto[1] 5 1 T266 1 T385 1 T371 1
auto[TlIntgErrBoth] partial auto[0] 36 1 T264 1 T265 1 T266 2
auto[TlIntgErrBoth] partial auto[1] 57 1 T264 4 T265 1 T266 1
auto[TlIntgErrBoth] full_word auto[0] 2 1 T264 1 T380 1 - -
auto[TlIntgErrBoth] full_word auto[1] 4 1 T264 1 T376 1 T383 1

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