Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T6,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T6,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T6,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T34
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T6,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T6,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T34
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T6,T20

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T6,T20

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1331501572	1328034636	0	0
CheckNGreaterZero_A	4104	4104	0	0
GntImpliesReady_A	1331501572	344136321	0	0
GntImpliesValid_A	1331501572	344136321	0	0
GrantKnown_A	1331501572	1328034636	0	0
IdxKnown_A	1331501572	1328034636	0	0
IndexIsCorrect_A	1331501572	344136321	0	0
NoReadyValidNoGrant_A	1331501572	172884599	0	0
Priority_A	1331501572	368260924	0	0
ReadyAndValidImplyGrant_A	1331501572	344136321	0	0
ReqAndReadyImplyGrant_A	1331501572	344136321	0	0
ReqImpliesValid_A	1331501572	368260924	0	0
ValidKnown_A	1331501572	1328034636	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	1328034636	0	0
T1	5900	5444	0	0
T2	14776	14400	0	0
T3	9132	8776	0	0
T4	17500	15408	0	0
T5	5000	4604	0	0
T6	3492	3104	0	0
T8	205128	204928	0	0
T15	3796	3544	0	0
T16	7336	6980	0	0
T17	7380	6984	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4104	4104	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T8	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	344136321	0	0
T1	2950	148	0	0
T2	7388	4438	0	0
T3	4566	356	0	0
T4	17500	576	0	0
T5	5000	520	0	0
T6	3492	96	0	0
T8	205128	2244	0	0
T9	4220	0	0	0
T10	2526	10	0	0
T11	0	6	0	0
T15	1898	64	0	0
T16	7336	356	0	0
T17	7380	356	0	0
T20	2210	0	0	0
T27	0	640	0	0
T33	0	888	0	0
T34	0	150	0	0
T59	2338	0	0	0
T64	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	344136321	0	0
T1	2950	148	0	0
T2	7388	4438	0	0
T3	4566	356	0	0
T4	17500	576	0	0
T5	5000	520	0	0
T6	3492	96	0	0
T8	205128	2244	0	0
T9	4220	0	0	0
T10	2526	10	0	0
T11	0	6	0	0
T15	1898	64	0	0
T16	7336	356	0	0
T17	7380	356	0	0
T20	2210	0	0	0
T27	0	640	0	0
T33	0	888	0	0
T34	0	150	0	0
T59	2338	0	0	0
T64	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	1328034636	0	0
T1	5900	5444	0	0
T2	14776	14400	0	0
T3	9132	8776	0	0
T4	17500	15408	0	0
T5	5000	4604	0	0
T6	3492	3104	0	0
T8	205128	204928	0	0
T15	3796	3544	0	0
T16	7336	6980	0	0
T17	7380	6984	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	1328034636	0	0
T1	5900	5444	0	0
T2	14776	14400	0	0
T3	9132	8776	0	0
T4	17500	15408	0	0
T5	5000	4604	0	0
T6	3492	3104	0	0
T8	205128	204928	0	0
T15	3796	3544	0	0
T16	7336	6980	0	0
T17	7380	6984	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	344136321	0	0
T1	2950	148	0	0
T2	7388	4438	0	0
T3	4566	356	0	0
T4	17500	576	0	0
T5	5000	520	0	0
T6	3492	96	0	0
T8	205128	2244	0	0
T9	4220	0	0	0
T10	2526	10	0	0
T11	0	6	0	0
T15	1898	64	0	0
T16	7336	356	0	0
T17	7380	356	0	0
T20	2210	0	0	0
T27	0	640	0	0
T33	0	888	0	0
T34	0	150	0	0
T59	2338	0	0	0
T64	0	200	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	172884599	0	0
T1	2950	512	0	0
T2	7388	256	0	0
T3	4566	696	0	0
T4	8750	1536	0	0
T5	2500	256	0	0
T6	3492	306	0	0
T8	205128	3554	0	0
T9	4220	0	0	0
T10	2526	20	0	0
T11	936	8	0	0
T15	1898	256	0	0
T16	7336	992	0	0
T17	7380	696	0	0
T19	0	268	0	0
T20	2210	0	0	0
T27	0	218	0	0
T33	3308	0	0	0
T34	0	52	0	0
T36	0	1116	0	0
T59	2338	0	0	0
T64	0	356	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	368260924	0	0
T1	2950	148	0	0
T2	7388	4438	0	0
T3	4566	356	0	0
T4	17500	576	0	0
T5	5000	520	0	0
T6	3492	96	0	0
T8	205128	2244	0	0
T9	4220	0	0	0
T10	2526	14	0	0
T11	0	6	0	0
T15	1898	64	0	0
T16	7336	356	0	0
T17	7380	356	0	0
T20	2210	0	0	0
T27	0	640	0	0
T33	0	888	0	0
T34	0	150	0	0
T59	2338	0	0	0
T64	0	200	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	344136321	0	0
T1	2950	148	0	0
T2	7388	4438	0	0
T3	4566	356	0	0
T4	17500	576	0	0
T5	5000	520	0	0
T6	3492	96	0	0
T8	205128	2244	0	0
T9	4220	0	0	0
T10	2526	10	0	0
T11	0	6	0	0
T15	1898	64	0	0
T16	7336	356	0	0
T17	7380	356	0	0
T20	2210	0	0	0
T27	0	640	0	0
T33	0	888	0	0
T34	0	150	0	0
T59	2338	0	0	0
T64	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	344136321	0	0
T1	2950	148	0	0
T2	7388	4438	0	0
T3	4566	356	0	0
T4	17500	576	0	0
T5	5000	520	0	0
T6	3492	96	0	0
T8	205128	2244	0	0
T9	4220	0	0	0
T10	2526	10	0	0
T11	0	6	0	0
T15	1898	64	0	0
T16	7336	356	0	0
T17	7380	356	0	0
T20	2210	0	0	0
T27	0	640	0	0
T33	0	888	0	0
T34	0	150	0	0
T59	2338	0	0	0
T64	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	368260924	0	0
T1	2950	148	0	0
T2	7388	4438	0	0
T3	4566	356	0	0
T4	17500	576	0	0
T5	5000	520	0	0
T6	3492	96	0	0
T8	205128	2244	0	0
T9	4220	0	0	0
T10	2526	14	0	0
T11	0	6	0	0
T15	1898	64	0	0
T16	7336	356	0	0
T17	7380	356	0	0
T20	2210	0	0	0
T27	0	640	0	0
T33	0	888	0	0
T34	0	150	0	0
T59	2338	0	0	0
T64	0	200	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1331501572	1328034636	0	0
T1	5900	5444	0	0
T2	14776	14400	0	0
T3	9132	8776	0	0
T4	17500	15408	0	0
T5	5000	4604	0	0
T6	3492	3104	0	0
T8	205128	204928	0	0
T15	3796	3544	0	0
T16	7336	6980	0	0
T17	7380	6984	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T6,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T6,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T6,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T6,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T6,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T6,T20

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T6,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	332875393	332008659	0	0
CheckNGreaterZero_A	1026	1026	0	0
GntImpliesReady_A	332875393	94983029	0	0
GntImpliesValid_A	332875393	94983029	0	0
GrantKnown_A	332875393	332008659	0	0
IdxKnown_A	332875393	332008659	0	0
IndexIsCorrect_A	332875393	94983029	0	0
NoReadyValidNoGrant_A	332875393	45095570	0	0
Priority_A	332875393	100971592	0	0
ReadyAndValidImplyGrant_A	332875393	94983029	0	0
ReqAndReadyImplyGrant_A	332875393	94983029	0	0
ReqImpliesValid_A	332875393	100971592	0	0
ValidKnown_A	332875393	332008659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	45095570	0	0
T1	1475	256	0	0
T2	3694	128	0	0
T3	2283	348	0	0
T4	4375	768	0	0
T5	1250	128	0	0
T6	873	153	0	0
T8	51282	836	0	0
T15	949	128	0	0
T16	1834	128	0	0
T17	1845	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	100971592	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	100971592	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T6,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T6,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T6,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T6,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T6,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T6,T20

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T6,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	332875393	332008659	0	0
CheckNGreaterZero_A	1026	1026	0	0
GntImpliesReady_A	332875393	94983029	0	0
GntImpliesValid_A	332875393	94983029	0	0
GrantKnown_A	332875393	332008659	0	0
IdxKnown_A	332875393	332008659	0	0
IndexIsCorrect_A	332875393	94983029	0	0
NoReadyValidNoGrant_A	332875393	45095570	0	0
Priority_A	332875393	100971592	0	0
ReadyAndValidImplyGrant_A	332875393	94983029	0	0
ReqAndReadyImplyGrant_A	332875393	94983029	0	0
ReqImpliesValid_A	332875393	100971592	0	0
ValidKnown_A	332875393	332008659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	45095570	0	0
T1	1475	256	0	0
T2	3694	128	0	0
T3	2283	348	0	0
T4	4375	768	0	0
T5	1250	128	0	0
T6	873	153	0	0
T8	51282	836	0	0
T15	949	128	0	0
T16	1834	128	0	0
T17	1845	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	100971592	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	94983029	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	100971592	0	0
T1	1475	74	0	0
T2	3694	2219	0	0
T3	2283	178	0	0
T4	4375	216	0	0
T5	1250	260	0	0
T6	873	48	0	0
T8	51282	502	0	0
T15	949	32	0	0
T16	1834	32	0	0
T17	1845	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T16,T8
1	0	Covered	T8,T10,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T10,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T10,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T34
1	0	Covered	T4,T16,T8
1	1	Covered	T8,T10,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T4,T16,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T34
1	1	Covered	T4,T16,T8

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T10,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T10,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	332875393	332008659	0	0
CheckNGreaterZero_A	1026	1026	0	0
GntImpliesReady_A	332875393	77085226	0	0
GntImpliesValid_A	332875393	77085226	0	0
GrantKnown_A	332875393	332008659	0	0
IdxKnown_A	332875393	332008659	0	0
IndexIsCorrect_A	332875393	77085226	0	0
NoReadyValidNoGrant_A	332875393	41346758	0	0
Priority_A	332875393	83158936	0	0
ReadyAndValidImplyGrant_A	332875393	77085226	0	0
ReqAndReadyImplyGrant_A	332875393	77085226	0	0
ReqImpliesValid_A	332875393	83158936	0	0
ValidKnown_A	332875393	332008659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085226	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085226	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085226	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	41346758	0	0
T6	873	0	0	0
T8	51282	941	0	0
T9	2110	0	0	0
T10	1263	10	0	0
T11	468	4	0	0
T16	1834	368	0	0
T17	1845	220	0	0
T19	0	134	0	0
T20	1105	0	0	0
T27	0	109	0	0
T33	1654	0	0	0
T34	0	26	0	0
T36	0	558	0	0
T59	1169	0	0	0
T64	0	178	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	83158936	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	7	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085226	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085226	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	83158936	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	7	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T4  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T4  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T4 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T4 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T16,T8
1	0	Covered	T8,T10,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T10,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T10,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T34
1	0	Covered	T4,T16,T8
1	1	Covered	T8,T10,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T4,T16,T8

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T34
1	1	Covered	T4,T16,T8

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T10,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T10,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	332875393	332008659	0	0
CheckNGreaterZero_A	1026	1026	0	0
GntImpliesReady_A	332875393	77085037	0	0
GntImpliesValid_A	332875393	77085037	0	0
GrantKnown_A	332875393	332008659	0	0
IdxKnown_A	332875393	332008659	0	0
IndexIsCorrect_A	332875393	77085037	0	0
NoReadyValidNoGrant_A	332875393	41346701	0	0
Priority_A	332875393	83158804	0	0
ReadyAndValidImplyGrant_A	332875393	77085037	0	0
ReqAndReadyImplyGrant_A	332875393	77085037	0	0
ReqImpliesValid_A	332875393	83158804	0	0
ValidKnown_A	332875393	332008659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085037	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085037	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085037	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	41346701	0	0
T6	873	0	0	0
T8	51282	941	0	0
T9	2110	0	0	0
T10	1263	10	0	0
T11	468	4	0	0
T16	1834	368	0	0
T17	1845	220	0	0
T19	0	134	0	0
T20	1105	0	0	0
T27	0	109	0	0
T33	1654	0	0	0
T34	0	26	0	0
T36	0	558	0	0
T59	1169	0	0	0
T64	0	178	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	83158804	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	7	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085037	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	77085037	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	5	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	83158804	0	0
T4	4375	72	0	0
T5	1250	0	0	0
T6	873	0	0	0
T8	51282	620	0	0
T9	2110	0	0	0
T10	1263	7	0	0
T11	0	3	0	0
T16	1834	146	0	0
T17	1845	146	0	0
T20	1105	0	0	0
T27	0	320	0	0
T33	0	444	0	0
T34	0	75	0	0
T59	1169	0	0	0
T64	0	100	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0