Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.33	100.00	89.30			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.33	100.00	89.30			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.33	100.00	89.30			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.33	100.00	89.30			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T6 T108 T109 
47         1/1                out_o.err <= '0;
           Tests:       T6 T108 T109 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T34 T27 
50         1/1                out_o.err <= '0;
           Tests:       T9 T34 T27 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T16 T8 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T16 T8 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T16 T8 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T16 T8 
56         1/1                out_o.err <= '0;
           Tests:       T3 T16 T8 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T16 T8 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T16 T8 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T16 T8 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T108,T109

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T8

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T34,T27

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T8

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T8

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T108,T109
0	0	1	-	-	Covered	T9,T34,T27
0	0	0	1	-	Covered	T3,T16,T8
0	0	0	0	1	Covered	T3,T16,T8
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	5288804	0	0
UpdateCheck_A	2147483647	5288790	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5288804	0	0
T3	9132	74	0	0
T4	17500	0	0	0
T5	5000	0	0	0
T6	6984	9	0	0
T8	410256	588	0	0
T9	16880	10	0	0
T10	5052	20	0	0
T11	1872	5	0	0
T15	3796	0	0	0
T16	14672	74	0	0
T17	14760	74	0	0
T19	0	132	0	0
T20	8840	5	0	0
T24	0	4	0	0
T27	0	119	0	0
T33	6616	0	0	0
T34	0	38	0	0
T36	0	186	0	0
T59	4676	0	0	0
T64	0	128	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5288790	0	0
T3	9132	74	0	0
T4	17500	0	0	0
T5	5000	0	0	0
T6	6984	9	0	0
T8	410256	588	0	0
T9	16880	10	0	0
T10	5052	20	0	0
T11	1872	4	0	0
T15	3796	0	0	0
T16	14672	74	0	0
T17	14760	74	0	0
T19	0	132	0	0
T20	8840	5	0	0
T24	0	9	0	0
T27	0	119	0	0
T33	6616	0	0	0
T34	0	38	0	0
T36	0	186	0	0
T59	4676	0	0	0
T64	0	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T6 T109 T110 
47         1/1                out_o.err <= '0;
           Tests:       T6 T109 T110 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T34 T27 
50         1/1                out_o.err <= '0;
           Tests:       T9 T34 T27 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T8 T6 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T8 T6 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T8 T6 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T8 T6 
56         1/1                out_o.err <= '0;
           Tests:       T3 T8 T6 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T8 T6 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T8 T6 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T8 T6 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T109,T110

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T34,T27

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T109,T110
0	0	1	-	-	Covered	T9,T34,T27
0	0	0	1	-	Covered	T3,T8,T6
0	0	0	0	1	Covered	T3,T8,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	703105	0	0
UpdateCheck_A	332875393	703105	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	703105	0	0
T3	2283	19	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	3	0	0
T8	51282	63	0	0
T9	2110	3	0	0
T10	0	4	0	0
T11	0	1	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T20	1105	2	0	0
T27	0	18	0	0
T34	0	9	0	0
T64	0	28	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	703105	0	0
T3	2283	19	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	3	0	0
T8	51282	63	0	0
T9	2110	3	0	0
T10	0	4	0	0
T11	0	1	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T20	1105	2	0	0
T27	0	18	0	0
T34	0	9	0	0
T64	0	28	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T6 T109 T110 
47         1/1                out_o.err <= '0;
           Tests:       T6 T109 T110 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T27 T36 
50         1/1                out_o.err <= '0;
           Tests:       T9 T27 T36 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T8 T6 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T8 T6 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T8 T6 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T8 T6 
56         1/1                out_o.err <= '0;
           Tests:       T3 T8 T6 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T8 T6 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T8 T6 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T8 T6 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T109,T110

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T27,T36

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T109,T110
0	0	1	-	-	Covered	T9,T27,T36
0	0	0	1	-	Covered	T3,T8,T6
0	0	0	0	1	Covered	T3,T8,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	702770	0	0
UpdateCheck_A	332875393	702768	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	702770	0	0
T3	2283	19	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	2	0	0
T8	51282	63	0	0
T9	2110	3	0	0
T10	0	4	0	0
T11	0	1	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T20	1105	1	0	0
T27	0	21	0	0
T34	0	7	0	0
T64	0	26	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	702768	0	0
T3	2283	19	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	2	0	0
T8	51282	63	0	0
T9	2110	3	0	0
T10	0	4	0	0
T11	0	1	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T20	1105	1	0	0
T27	0	21	0	0
T34	0	7	0	0
T64	0	26	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T6 T109 T110 
47         1/1                out_o.err <= '0;
           Tests:       T6 T109 T110 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T27 T36 
50         1/1                out_o.err <= '0;
           Tests:       T9 T27 T36 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T8 T6 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T8 T6 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T8 T6 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T8 T6 
56         1/1                out_o.err <= '0;
           Tests:       T3 T8 T6 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T8 T6 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T8 T6 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T8 T6 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T109,T110

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T27,T36

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T109,T110
0	0	1	-	-	Covered	T9,T27,T36
0	0	0	1	-	Covered	T3,T8,T6
0	0	0	0	1	Covered	T3,T8,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	702538	0	0
UpdateCheck_A	332875393	702534	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	702538	0	0
T3	2283	18	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	2	0	0
T8	51282	62	0	0
T9	2110	2	0	0
T10	0	4	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T19	0	8	0	0
T20	1105	1	0	0
T27	0	23	0	0
T34	0	7	0	0
T64	0	24	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	702534	0	0
T3	2283	18	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	2	0	0
T8	51282	62	0	0
T9	2110	2	0	0
T10	0	4	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T19	0	8	0	0
T20	1105	1	0	0
T27	0	23	0	0
T34	0	7	0	0
T64	0	24	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T6 T109 T110 
47         1/1                out_o.err <= '0;
           Tests:       T6 T109 T110 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T27 T36 
50         1/1                out_o.err <= '0;
           Tests:       T9 T27 T36 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T8 T6 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T8 T6 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T8 T6 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T8 T6 
56         1/1                out_o.err <= '0;
           Tests:       T3 T8 T6 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T8 T6 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T8 T6 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T8 T6 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T109,T110

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T27,T36

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T109,T110
0	0	1	-	-	Covered	T9,T27,T36
0	0	0	1	-	Covered	T3,T8,T6
0	0	0	0	1	Covered	T3,T8,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	702306	0	0
UpdateCheck_A	332875393	702305	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	702306	0	0
T3	2283	18	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	2	0	0
T8	51282	62	0	0
T9	2110	2	0	0
T10	0	3	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T19	0	8	0	0
T20	1105	1	0	0
T27	0	20	0	0
T34	0	7	0	0
T64	0	24	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	702305	0	0
T3	2283	18	0	0
T4	4375	0	0	0
T5	1250	0	0	0
T6	873	2	0	0
T8	51282	62	0	0
T9	2110	2	0	0
T10	0	3	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T19	0	8	0	0
T20	1105	1	0	0
T27	0	20	0	0
T34	0	7	0	0
T64	0	24	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T108 T109 T111 
47         1/1                out_o.err <= '0;
           Tests:       T108 T109 T111 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T24 T28 T92 
50         1/1                out_o.err <= '0;
           Tests:       T24 T28 T92 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T16 T8 T17 
53         1/1                out_o.part <= part_i;
           Tests:       T16 T8 T17 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T16 T8 T17 
55         1/1                out_o.attr <= Wip;
           Tests:       T16 T8 T17 
56         1/1                out_o.err <= '0;
           Tests:       T16 T8 T17 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T16 T8 T17 
59         1/1                out_o.attr <= Valid;
           Tests:       T16 T8 T17 
60         1/1                out_o.err <= err_i;
           Tests:       T16 T8 T17 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T8,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T108,T109,T111

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T8,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T24,T28,T92

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T108,T109,T111
0	0	1	-	-	Covered	T24,T28,T92
0	0	0	1	-	Covered	T16,T8,T17
0	0	0	0	1	Covered	T16,T8,T17
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	619982	0	0
UpdateCheck_A	332875393	619979	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619982	0	0
T6	873	0	0	0
T8	51282	85	0	0
T9	2110	0	0	0
T10	1263	2	0	0
T11	468	1	0	0
T16	1834	19	0	0
T17	1845	19	0	0
T19	0	29	0	0
T20	1105	0	0	0
T27	0	10	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	47	0	0
T59	1169	0	0	0
T64	0	7	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619979	0	0
T6	873	0	0	0
T8	51282	85	0	0
T9	2110	0	0	0
T10	1263	2	0	0
T11	468	1	0	0
T16	1834	19	0	0
T17	1845	19	0	0
T19	0	29	0	0
T20	1105	0	0	0
T27	0	10	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	47	0	0
T59	1169	0	0	0
T64	0	7	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T108 T109 T111 
47         1/1                out_o.err <= '0;
           Tests:       T108 T109 T111 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T24 T28 T92 
50         1/1                out_o.err <= '0;
           Tests:       T24 T28 T92 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T16 T8 T17 
53         1/1                out_o.part <= part_i;
           Tests:       T16 T8 T17 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T16 T8 T17 
55         1/1                out_o.attr <= Wip;
           Tests:       T16 T8 T17 
56         1/1                out_o.err <= '0;
           Tests:       T16 T8 T17 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T16 T8 T17 
59         1/1                out_o.attr <= Valid;
           Tests:       T16 T8 T17 
60         1/1                out_o.err <= err_i;
           Tests:       T16 T8 T17 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T8,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T108,T109,T111

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T8,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T24,T28,T92

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T108,T109,T111
0	0	1	-	-	Covered	T24,T28,T92
0	0	0	1	-	Covered	T16,T8,T17
0	0	0	0	1	Covered	T16,T8,T17
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	619754	0	0
UpdateCheck_A	332875393	619752	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619754	0	0
T6	873	0	0	0
T8	51282	85	0	0
T9	2110	0	0	0
T10	1263	1	0	0
T11	468	1	0	0
T16	1834	19	0	0
T17	1845	19	0	0
T19	0	30	0	0
T20	1105	0	0	0
T27	0	9	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	47	0	0
T59	1169	0	0	0
T64	0	7	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619752	0	0
T6	873	0	0	0
T8	51282	85	0	0
T9	2110	0	0	0
T10	1263	1	0	0
T11	468	1	0	0
T16	1834	19	0	0
T17	1845	19	0	0
T19	0	30	0	0
T20	1105	0	0	0
T27	0	9	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	47	0	0
T59	1169	0	0	0
T64	0	7	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T108 T109 T111 
47         1/1                out_o.err <= '0;
           Tests:       T108 T109 T111 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T24 T28 T92 
50         1/1                out_o.err <= '0;
           Tests:       T24 T28 T92 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T16 T8 T17 
53         1/1                out_o.part <= part_i;
           Tests:       T16 T8 T17 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T16 T8 T17 
55         1/1                out_o.attr <= Wip;
           Tests:       T16 T8 T17 
56         1/1                out_o.err <= '0;
           Tests:       T16 T8 T17 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T16 T8 T17 
59         1/1                out_o.attr <= Valid;
           Tests:       T16 T8 T17 
60         1/1                out_o.err <= err_i;
           Tests:       T16 T8 T17 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T8,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T108,T109,T111

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T8,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T24,T28,T92

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T108,T109,T111
0	0	1	-	-	Covered	T24,T28,T92
0	0	0	1	-	Covered	T16,T8,T17
0	0	0	0	1	Covered	T16,T8,T17
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	619320	0	0
UpdateCheck_A	332875393	619318	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619320	0	0
T6	873	0	0	0
T8	51282	84	0	0
T9	2110	0	0	0
T10	1263	1	0	0
T11	468	1	0	0
T16	1834	18	0	0
T17	1845	18	0	0
T19	0	29	0	0
T20	1105	0	0	0
T27	0	9	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	46	0	0
T59	1169	0	0	0
T64	0	6	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619318	0	0
T6	873	0	0	0
T8	51282	84	0	0
T9	2110	0	0	0
T10	1263	1	0	0
T11	468	0	0	0
T16	1834	18	0	0
T17	1845	18	0	0
T19	0	29	0	0
T20	1105	0	0	0
T24	0	5	0	0
T27	0	9	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	46	0	0
T59	1169	0	0	0
T64	0	6	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T109 T111 T110 
47         1/1                out_o.err <= '0;
           Tests:       T109 T111 T110 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T24 T28 T92 
50         1/1                out_o.err <= '0;
           Tests:       T24 T28 T92 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T16 T8 T17 
53         1/1                out_o.part <= part_i;
           Tests:       T16 T8 T17 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T16 T8 T17 
55         1/1                out_o.attr <= Wip;
           Tests:       T16 T8 T17 
56         1/1                out_o.err <= '0;
           Tests:       T16 T8 T17 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T16 T8 T17 
59         1/1                out_o.attr <= Valid;
           Tests:       T16 T8 T17 
60         1/1                out_o.err <= err_i;
           Tests:       T16 T8 T17 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T16,T8,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T109,T111,T110

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T8,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T24,T28,T92

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T8,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T109,T111,T110
0	0	1	-	-	Covered	T24,T28,T92
0	0	0	1	-	Covered	T16,T8,T17
0	0	0	0	1	Covered	T16,T8,T17
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	332875393	619029	0	0
UpdateCheck_A	332875393	619029	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619029	0	0
T6	873	0	0	0
T8	51282	84	0	0
T9	2110	0	0	0
T10	1263	1	0	0
T11	468	0	0	0
T16	1834	18	0	0
T17	1845	18	0	0
T19	0	28	0	0
T20	1105	0	0	0
T24	0	4	0	0
T27	0	9	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	46	0	0
T59	1169	0	0	0
T64	0	6	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	619029	0	0
T6	873	0	0	0
T8	51282	84	0	0
T9	2110	0	0	0
T10	1263	1	0	0
T11	468	0	0	0
T16	1834	18	0	0
T17	1845	18	0	0
T19	0	28	0	0
T20	1105	0	0	0
T24	0	4	0	0
T27	0	9	0	0
T33	1654	0	0	0
T34	0	2	0	0
T36	0	46	0	0
T59	1169	0	0	0
T64	0	6	0	0