Module Definition
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Module Instance : tb.dut.u_flash_ctrl_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 97.06 94.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.88 100.00 97.06 100.00 94.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cnt 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
TOTAL5454100.00
ALWAYS5533100.00
ALWAYS9044100.00
CONT_ASSIGN9711100.00
CONT_ASSIGN9811100.00
ALWAYS10155100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
ALWAYS1322626100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19311100.00

54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 st_q <= StNorm; Tests: T1 T2 T3  57 end else begin 58 1/1 st_q <= st_d; Tests: T1 T2 T3  59 end 60 end 61 62 //always_ff @(posedge clk_i or negedge rst_ni) begin 63 // if (!rst_ni) begin 64 // cnt <= '0; 65 // end else if (op_start_i && op_done_o) begin 66 // cnt <= '0; 67 // end else if (data_rd_o) begin 68 // cnt <= cnt + 1'b1; 69 // end 70 //end 71 72 prim_count #( 73 .Width(12) 74 ) u_cnt ( 75 .clk_i, 76 .rst_ni, 77 .clr_i(op_start_i && op_done_o), 78 .set_i('0), 79 .set_cnt_i('0), 80 .incr_en_i(data_rd_o), 81 .decr_en_i(1'b0), 82 .step_i(12'h1), 83 .commit_i(1'b1), 84 .cnt_o(cnt), 85 .cnt_after_commit_o(), 86 .err_o(cnt_err_o) 87 ); 88 89 always_ff @(posedge clk_i or negedge rst_ni) begin 90 1/1 if (!rst_ni) begin Tests: T1 T2 T3  91 1/1 op_err_addr_o <= '0; Tests: T1 T2 T3  92 1/1 end else if (~|op_err_q && |op_err_d) begin Tests: T1 T2 T3  93 1/1 op_err_addr_o <= flash_addr_o; Tests: T4 T37 T51  94 end MISSING_ELSE 95 end 96 97 1/1 assign txn_done = flash_req_o && flash_done_i; Tests: T1 T2 T3  98 1/1 assign cnt_hit = (cnt >= op_num_words_i); Tests: T1 T2 T3  99 100 always_ff @(posedge clk_i or negedge rst_ni) begin 101 1/1 if (!rst_ni) begin Tests: T1 T2 T3  102 1/1 op_err_q <= '0; Tests: T1 T2 T3  103 1/1 end else if (op_start_i && op_done_o) begin Tests: T1 T2 T3  104 1/1 op_err_q <= '0; Tests: T2 T4 T5  105 end else begin 106 1/1 op_err_q <= op_err_d; Tests: T1 T2 T3  107 end 108 end 109 110 // if the requested prog type is available 111 logic prog_type_avail; 112 1/1 assign prog_type_avail = type_avail_i[op_type_i]; Tests: T1 T2 T3  113 114 // program resolution check 115 // if the incoming beat is larger than the maximum program resolution, error 116 // immediately and do not allow it to start. 117 localparam int WindowWidth = BusAddrW - BusPgmResWidth; 118 logic [WindowWidth-1:0] start_window, end_window; 119 logic [BusAddrW-1:0] end_addr; 120 logic pgm_res_err; 121 logic win_err; 122 1/1 assign end_addr = op_addr_i + BusAddrW'(op_num_words_i); Tests: T1 T2 T3  123 1/1 assign start_window = op_addr_i[BusAddrW-1:BusPgmResWidth]; Tests: T1 T2 T3  124 1/1 assign end_window = end_addr[BusAddrW-1:BusPgmResWidth]; Tests: T1 T2 T3  125 1/1 assign pgm_res_err = start_window != end_window; Tests: T1 T2 T3  126 1/1 assign win_err = pgm_res_err | op_addr_oob_i; Tests: T1 T2 T3  127 128 // when error'd, continue to drain all program fifo contents like normal operation 129 // if this is not done, software may fill up the fifo without anyone 130 // draining the contents, leading to a lockup 131 always_comb begin 132 1/1 st_d = st_q; Tests: T1 T2 T3  133 1/1 flash_req_o = 1'b0; Tests: T1 T2 T3  134 1/1 data_rd_o = 1'b0; Tests: T1 T2 T3  135 1/1 op_done_o = 1'b0; Tests: T1 T2 T3  136 1/1 op_err_d = op_err_q; Tests: T1 T2 T3  137 138 1/1 unique case (st_q) Tests: T1 T2 T3  139 140 // Note the address counter is incremented on tx_done 141 // and cleared when the entire operation is complete. 142 StNorm: begin 143 144 1/1 if (cnt_err_o) begin Tests: T1 T2 T3  145 // if count error'd don't bother doing anything else, just try to finish 146 1/1 st_d = StErr; Tests: T12 T13 T14  147 148 1/1 end else if (op_start_i && prog_type_avail && !win_err) begin Tests: T1 T2 T3  149 // if the select operation type is not available, error 150 1/1 flash_req_o = data_rdy_i; Tests: T1 T2 T4  151 152 1/1 if (txn_done) begin Tests: T1 T2 T4  153 1/1 op_err_d.mp_err = flash_mp_err_i; Tests: T1 T2 T4  154 1/1 op_err_d.prog_err = flash_prog_intg_err_i; Tests: T1 T2 T4  155 1/1 data_rd_o = 1'b1; Tests: T1 T2 T4  156 157 1/1 if (cnt_hit) begin Tests: T1 T2 T4  158 1/1 op_done_o = 1'b1; Tests: T2 T4 T5  159 end else begin 160 1/1 st_d = |op_err_d ? StErr : StNorm; Tests: T1 T2 T4  161 end 162 end MISSING_ELSE 163 164 1/1 end else if (op_start_i && (!prog_type_avail || win_err)) begin Tests: T1 T2 T3  165 1/1 op_err_d.oob_err = op_addr_oob_i; Tests: T57 T166 T223  166 1/1 op_err_d.prog_type_err = !prog_type_avail; Tests: T57 T166 T223  167 1/1 op_err_d.prog_win_err = pgm_res_err; Tests: T57 T166 T223  168 1/1 st_d = StErr; Tests: T57 T166 T223  169 end MISSING_ELSE 170 end 171 StErr: begin 172 1/1 data_rd_o = data_rdy_i; Tests: T4 T37 T51  173 174 1/1 if (data_rdy_i && cnt_hit) begin Tests: T4 T37 T51  175 1/1 st_d = StNorm; Tests: T37 T51 T42  176 1/1 op_done_o = 1'b1; Tests: T37 T51 T42  177 end MISSING_ELSE 178 end 179 default:; 180 endcase // unique case (st) 181 end 182 183 1/1 assign flash_data_o = data_i; Tests: T1 T2 T3  184 1/1 assign int_addr = op_addr_i + BusAddrW'(cnt); Tests: T1 T2 T3  185 1/1 assign flash_addr_o = int_addr[0 +: BusAddrW]; Tests: T1 T2 T3  186 1/1 assign flash_ovfl_o = int_addr[BusAddrW]; Tests: T1 T2 T3  187 1/1 assign flash_last_o = flash_req_o & cnt_hit; Tests: T1 T2 T3  188 1/1 assign flash_type_o = op_type_i; Tests: T1 T2 T3  189 1/1 assign op_err_o = op_err_q | op_err_d; Tests: T1 T2 T3  190 191 // unused signals 192 logic [BusPgmResWidth-1:0] unused_end_addr; 193 1/1 assign unused_end_addr = end_addr[BusPgmResWidth-1:0]; Tests: T1 T2 T3 

Cond Coverage for Module : flash_ctrl_prog
TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       74
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT142,T183,T146
10CoveredT1,T2,T4
11CoveredT2,T4,T5

 LINE       92
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------
-1--2-StatusTests
01CoveredT4,T37,T51
10CoveredT1,T2,T3
11CoveredT4,T37,T51

 LINE       97
 EXPRESSION (flash_req_o && flash_done_i)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT59,T10,T27
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       103
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT142,T183,T146
10CoveredT1,T2,T4
11CoveredT2,T4,T5

 LINE       125
 EXPRESSION (start_window != end_window)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T16

 LINE       126
 EXPRESSION (pgm_res_err | op_addr_oob_i)
             -----1-----   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T16

 LINE       148
 EXPRESSION (op_start_i && prog_type_avail && ((!win_err)))
             -----1----    -------2-------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT114,T115,T116
110CoveredT57,T166,T223
111CoveredT1,T2,T4

 LINE       160
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT4,T37,T51

 LINE       164
 EXPRESSION (op_start_i && (((!prog_type_avail)) || win_err))
             -----1----    ----------------2----------------
-1--2-StatusTests
01CoveredT2,T3,T16
10Not Covered
11CoveredT57,T166,T223

 LINE       164
 SUB-EXPRESSION (((!prog_type_avail)) || win_err)
                 ----------1---------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T16
10CoveredT114,T115,T116

 LINE       174
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT4,T37,T51
10CoveredT4,T37,T51
11CoveredT37,T51,T42

 LINE       187
 EXPRESSION (flash_req_o & cnt_hit)
             -----1-----   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT2,T4,T5

Branch Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
Branches 18 17 94.44
IF 55 2 2 100.00
IF 90 3 3 100.00
IF 101 3 3 100.00
CASE 138 10 9 90.00


55 if (!rst_ni) begin -1- 56 st_q <= StNorm; ==> 57 end else begin 58 st_q <= st_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


90 if (!rst_ni) begin -1- 91 op_err_addr_o <= '0; ==> 92 end else if (~|op_err_q && |op_err_d) begin -2- 93 op_err_addr_o <= flash_addr_o; ==> 94 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T4,T37,T51
0 0 Covered T1,T2,T3


101 if (!rst_ni) begin -1- 102 op_err_q <= '0; ==> 103 end else if (op_start_i && op_done_o) begin -2- 104 op_err_q <= '0; ==> 105 end else begin 106 op_err_q <= op_err_d; ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T4,T5
0 0 Covered T1,T2,T3


138 unique case (st_q) -1- 139 140 // Note the address counter is incremented on tx_done 141 // and cleared when the entire operation is complete. 142 StNorm: begin 143 144 if (cnt_err_o) begin -2- 145 // if count error'd don't bother doing anything else, just try to finish 146 st_d = StErr; ==> 147 148 end else if (op_start_i && prog_type_avail && !win_err) begin -3- 149 // if the select operation type is not available, error 150 flash_req_o = data_rdy_i; 151 152 if (txn_done) begin -4- 153 op_err_d.mp_err = flash_mp_err_i; 154 op_err_d.prog_err = flash_prog_intg_err_i; 155 data_rd_o = 1'b1; 156 157 if (cnt_hit) begin -5- 158 op_done_o = 1'b1; ==> 159 end else begin 160 st_d = |op_err_d ? StErr : StNorm; -6- ==> ==> 161 end 162 end MISSING_ELSE ==> 163 164 end else if (op_start_i && (!prog_type_avail || win_err)) begin -7- 165 op_err_d.oob_err = op_addr_oob_i; ==> 166 op_err_d.prog_type_err = !prog_type_avail; 167 op_err_d.prog_win_err = pgm_res_err; 168 st_d = StErr; 169 end MISSING_ELSE ==> 170 end 171 StErr: begin 172 data_rd_o = data_rdy_i; 173 174 if (data_rdy_i && cnt_hit) begin -8- 175 st_d = StNorm; ==> 176 op_done_o = 1'b1; 177 end MISSING_ELSE ==> 178 end 179 default:; ==>

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StNorm 1 - - - - - - Covered T12,T13,T14
StNorm 0 1 1 1 - - - Covered T2,T4,T5
StNorm 0 1 1 0 1 - - Covered T4,T37,T51
StNorm 0 1 1 0 0 - - Covered T1,T2,T4
StNorm 0 1 0 - - - - Covered T1,T2,T4
StNorm 0 0 - - - 1 - Covered T57,T166,T223
StNorm 0 0 - - - 0 - Covered T1,T2,T3
StErr - - - - - - 1 Covered T37,T51,T42
StErr - - - - - - 0 Covered T4,T37,T51
default - - - - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%