Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.03	97.43	96.67			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	71.04	90.91	66.67			55.56
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt	71.04	90.91	66.67			55.56
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt	80.19	100.00	73.91			66.67
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	80.19	100.00	73.91			66.67
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73
tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt	92.40	92.59	100.00			84.62
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt	97.10	100.00	91.30			100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	97.10	100.00	91.30			100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt	97.10	100.00	91.30			100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt	97.10	100.00	91.30			100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt	97.10	100.00	91.30			100.00
tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
81.58	92.00

tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
71.04	90.91

tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
71.04	90.91

tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		25	23	92.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	7	6	85.71
ALWAYS	125	7	6	85.71

40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        unreachable          wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T1 T2 T4 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        0/1     ==>          wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        unreachable          rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T1 T2 T4 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        0/1     ==>          rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
133                           end
                        MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=1,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
80.19	100.00

tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
80.19	100.00

tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
97.10	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
97.10	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		12	12	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	109	1	1	100.00

40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109        1/1              assign err_o = wptr_err | rptr_err;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	8	8	100.00
ALWAYS	125	8	8	100.00

40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T2 T4 T5 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T2 T4 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T2 T4 T5 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T2 T4 
133                           end
                        MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=16,Secure=0,PtrW=4,DepthW=5,WrapPtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
92.40	92.59

tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		27	25	92.59
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	8	7	87.50
ALWAYS	125	8	7	87.50

40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        0/1     ==>          wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T3 T16 T8 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T3 T16 T8 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        0/1     ==>          rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T3 T16 T8 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T3 T16 T8 
133                           end
                        MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
93.64	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
93.64	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
ALWAYS	113	7	7	100.00
ALWAYS	125	7	7	100.00

40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109                         assign err_o = wptr_err | rptr_err;
110                     
111                       end else begin : gen_normal_ptrs
112                         always_ff @(posedge clk_i or negedge rst_ni) begin
113        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
114        1/1                  wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
115        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
116        unreachable          wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
117        1/1                end else if (wptr_wrap_set) begin
           Tests:       T1 T2 T3 
118        1/1                  wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
           Tests:       T1 T2 T3 
119        1/1                end else if (incr_wptr_i) begin
           Tests:       T1 T2 T3 
120        1/1                  wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T2 T3 
121                           end
                        MISSING_ELSE
122                         end
123                     
124                         always_ff @(posedge clk_i or negedge rst_ni) begin
125        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
126        1/1                  rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
           Tests:       T1 T2 T3 
127        1/1                end else if (clr_i) begin
           Tests:       T1 T2 T3 
128        unreachable          rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
129        1/1                end else if (rptr_wrap_set) begin
           Tests:       T1 T2 T3 
130        1/1                  rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
           Tests:       T1 T2 T3 
131        1/1                end else if (incr_rptr_i) begin
           Tests:       T1 T2 T3 
132        1/1                  rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
           Tests:       T1 T2 T3 
133                           end
                        MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
97.10	100.00

tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
97.10	100.00

tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
97.10	100.00

tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		12	12	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	109	1	1	100.00

40                        // Derive real read and write pointers by truncating the internal 'wrap' pointers.
41         1/1            assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
42         1/1            assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0];
           Tests:       T1 T2 T3 
43                      
44                        // Extract the MSB of the 'wrap' pointers.
45                        logic wptr_wrap_msb, rptr_wrap_msb;
46         1/1            assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
47         1/1            assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1];
           Tests:       T1 T2 T3 
48                      
49                        // Wrap pointers when they have reached the maximum value and are about to get incremented.
50                        logic wptr_wrap_set, rptr_wrap_set;
51         1/1            assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
52         1/1            assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1));
           Tests:       T1 T2 T3 
53                      
54                        // When wrapping, invert the MSB and reset all lower bits to zero.
55         1/1            assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
56         1/1            assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}};
           Tests:       T1 T2 T3 
57                      
58                        // Full when both 'wrap' counters have a different MSB but all lower bits are equal.
59         1/1            assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}});
           Tests:       T1 T2 T3 
60                        // Empty when both 'wrap' counters are equal in all bits including the MSB.
61         1/1            assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q;
           Tests:       T1 T2 T3 
62                      
63                        // The current depth is equal to:
64                        // - when full: the maximum depth;
65                        // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers;
66                        // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference
67                        //   of the real pointers.
68         1/1            assign depth_o = full_o                         ? DepthW'(Depth) :
           Tests:       T1 T2 T3 
69                                         wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
70                                         DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o);
71                      
72                        if (Secure) begin : gen_secure_ptrs
73                          logic wptr_err;
74                          prim_count #(
75                            .Width(WrapPtrW)
76                          ) u_wptr (
77                            .clk_i,
78                            .rst_ni,
79                            .clr_i,
80                            .set_i(wptr_wrap_set),
81                            .set_cnt_i(wptr_wrap_set_cnt),
82                            .incr_en_i(incr_wptr_i),
83                            .decr_en_i(1'b0),
84                            .step_i(WrapPtrW'(1'b1)),
85                            .commit_i(1'b1),
86                            .cnt_o(wptr_wrap_cnt_q),
87                            .cnt_after_commit_o(),
88                            .err_o(wptr_err)
89                          );
90                      
91                          logic rptr_err;
92                          prim_count #(
93                            .Width(WrapPtrW)
94                          ) u_rptr (
95                            .clk_i,
96                            .rst_ni,
97                            .clr_i,
98                            .set_i(rptr_wrap_set),
99                            .set_cnt_i(rptr_wrap_set_cnt),
100                           .incr_en_i(incr_rptr_i),
101                           .decr_en_i(1'b0),
102                           .step_i(WrapPtrW'(1'b1)),
103                           .commit_i(1'b1),
104                           .cnt_o(rptr_wrap_cnt_q),
105                           .cnt_after_commit_o(),
106                           .err_o(rptr_err)
107                         );
108                     
109        1/1              assign err_o = wptr_err | rptr_err;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=1,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
80.19	73.91

tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
80.19	73.91

tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
97.10	91.30

tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
97.10	91.30

tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	23	23	100.00
Logical	23	23	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T72
1	1	Covered	T3,T5,T16

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T72
1	1	Covered	T3,T5,T16

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T16

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T16

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T14,T72
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T14,T72
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=16,Secure=0,PtrW=4,DepthW=5,WrapPtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
92.40	100.00

tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T8
1	0	Covered	T3,T16,T8
1	1	Covered	T3,T16,T8

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T8

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T8
1	0	Covered	T3,T16,T8
1	1	Covered	T3,T16,T8

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T8

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T43,T44

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (5'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((5'(wptr_o) - 5'(rptr_o))) : (((5'(Depth) - 5'(rptr_o)) + 5'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T43,T44

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((5'(wptr_o) - 5'(rptr_o))) : (((5'(Depth) - 5'(rptr_o)) + 5'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T16,T8
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T3,T16,T8
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
97.10	91.30

tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
97.10	91.30

tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
97.10	91.30

tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	23	23	100.00
Logical	23	23	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T10,T11

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T10,T11

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       51
 SUB-EXPRESSION (wptr_o == 2'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       52
 SUB-EXPRESSION (rptr_o == 2'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (3'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
81.58	80.00

tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
71.04	66.67

tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
71.04	66.67

tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	16	80.00
Logical	20	16	80.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	COND
93.64	90.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt

SCORE	COND
93.64	90.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORE	COND
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	20	20	100.00
Logical	20	20	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 + Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 + Depth=16,Secure=0,PtrW=4,DepthW=5,WrapPtrW=5 + Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
81.58	72.73

tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
71.04	55.56

tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
71.04	55.56

tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
92.40	84.62

tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
93.64	90.91

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
93.64	90.91

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	68	3	3	100.00
IF	113	5	5	100.00
IF	125	5	5	100.00

68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

113              if (!rst_ni) begin
                 -1-  
114                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
115              end else if (clr_i) begin
                          -2-  
116                wptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
117              end else if (wptr_wrap_set) begin
                          -3-  
118                wptr_wrap_cnt_q <= wptr_wrap_set_cnt;
                   ==>
119              end else if (incr_wptr_i) begin
                          -4-  
120                wptr_wrap_cnt_q <= wptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
121              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

125              if (!rst_ni) begin
                 -1-  
126                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
127              end else if (clr_i) begin
                          -2-  
128                rptr_wrap_cnt_q <= {WrapPtrW{1'b0}};
                   ==>
129              end else if (rptr_wrap_set) begin
                          -3-  
130                rptr_wrap_cnt_q <= rptr_wrap_set_cnt;
                   ==>
131              end else if (incr_rptr_i) begin
                          -4-  
132                rptr_wrap_cnt_q <= rptr_wrap_cnt_q + {{(WrapPtrW-1){1'b0}}, 1'b1};
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=1,PtrW=1,DepthW=1,WrapPtrW=2 + Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
80.19	66.67

tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
80.19	66.67

tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
97.10	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
97.10	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
97.10	100.00

tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
97.10	100.00

tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
97.10	100.00

tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	BRANCH
100.00	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
TERNARY	68	3	3	100.00

68           assign depth_o = full_o                         ? DepthW'(Depth) :
                                                             -1-  
                                                             ==>  
69                            wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) :
                                                             -2-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T8,T6,T20