Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	335615710	4537	0	0
addr_rd_A	335615710	1619	0	0
bank0_info0_page_cfg_0_rd_A	335615710	2751	0	0
bank0_info0_page_cfg_1_rd_A	335615710	2749	0	0
bank0_info0_page_cfg_2_rd_A	335615710	3030	0	0
bank0_info0_page_cfg_3_rd_A	335615710	2908	0	0
bank0_info0_page_cfg_4_rd_A	335615710	2922	0	0
bank0_info0_page_cfg_5_rd_A	335615710	2814	0	0
bank0_info0_page_cfg_6_rd_A	335615710	2742	0	0
bank0_info0_page_cfg_7_rd_A	335615710	2889	0	0
bank0_info0_page_cfg_8_rd_A	335615710	2783	0	0
bank0_info0_page_cfg_9_rd_A	335615710	2846	0	0
bank0_info0_regwen_0_rd_A	335615710	1721	0	0
bank0_info0_regwen_1_rd_A	335615710	1649	0	0
bank0_info0_regwen_2_rd_A	335615710	1563	0	0
bank0_info0_regwen_3_rd_A	335615710	1801	0	0
bank0_info0_regwen_4_rd_A	335615710	1640	0	0
bank0_info0_regwen_5_rd_A	335615710	1720	0	0
bank0_info0_regwen_6_rd_A	335615710	1744	0	0
bank0_info0_regwen_7_rd_A	335615710	1563	0	0
bank0_info0_regwen_8_rd_A	335615710	1627	0	0
bank0_info0_regwen_9_rd_A	335615710	1759	0	0
bank0_info1_page_cfg_rd_A	335615710	2862	0	0
bank0_info1_regwen_rd_A	335615710	1569	0	0
bank0_info2_page_cfg_0_rd_A	335615710	2905	0	0
bank0_info2_page_cfg_1_rd_A	335615710	3017	0	0
bank0_info2_regwen_0_rd_A	335615710	1555	0	0
bank0_info2_regwen_1_rd_A	335615710	1655	0	0
bank1_info0_page_cfg_0_rd_A	335615710	2899	0	0
bank1_info0_page_cfg_1_rd_A	335615710	2770	0	0
bank1_info0_page_cfg_2_rd_A	335615710	2836	0	0
bank1_info0_page_cfg_3_rd_A	335615710	3158	0	0
bank1_info0_page_cfg_4_rd_A	335615710	2664	0	0
bank1_info0_page_cfg_5_rd_A	335615710	2612	0	0
bank1_info0_page_cfg_6_rd_A	335615710	2856	0	0
bank1_info0_page_cfg_7_rd_A	335615710	2601	0	0
bank1_info0_page_cfg_8_rd_A	335615710	3056	0	0
bank1_info0_page_cfg_9_rd_A	335615710	2386	0	0
bank1_info0_regwen_0_rd_A	335615710	1638	0	0
bank1_info0_regwen_1_rd_A	335615710	1697	0	0
bank1_info0_regwen_2_rd_A	335615710	1636	0	0
bank1_info0_regwen_3_rd_A	335615710	1694	0	0
bank1_info0_regwen_4_rd_A	335615710	1638	0	0
bank1_info0_regwen_5_rd_A	335615710	1555	0	0
bank1_info0_regwen_6_rd_A	335615710	1653	0	0
bank1_info0_regwen_7_rd_A	335615710	1619	0	0
bank1_info0_regwen_8_rd_A	335615710	1611	0	0
bank1_info0_regwen_9_rd_A	335615710	1720	0	0
bank1_info1_page_cfg_rd_A	335615710	2998	0	0
bank1_info1_regwen_rd_A	335615710	1685	0	0
bank1_info2_page_cfg_0_rd_A	335615710	2710	0	0
bank1_info2_page_cfg_1_rd_A	335615710	2951	0	0
bank1_info2_regwen_0_rd_A	335615710	1768	0	0
bank1_info2_regwen_1_rd_A	335615710	1685	0	0
bank_cfg_regwen_rd_A	335615710	1718	0	0
default_region_rd_A	335615710	2601	0	0
exec_rd_A	335615710	1646	0	0
fifo_lvl_rd_A	335615710	1790	0	0
fifo_rst_rd_A	335615710	1626	0	0
hw_info_cfg_override_rd_A	335615710	1990	0	0
intr_enable_rd_A	335615710	2448	0	0
mp_region_0_rd_A	335615710	1867	0	0
mp_region_1_rd_A	335615710	1859	0	0
mp_region_2_rd_A	335615710	2087	0	0
mp_region_3_rd_A	335615710	1939	0	0
mp_region_4_rd_A	335615710	1949	0	0
mp_region_5_rd_A	335615710	1802	0	0
mp_region_6_rd_A	335615710	1791	0	0
mp_region_7_rd_A	335615710	1823	0	0
mp_region_cfg_0_rd_A	335615710	3036	0	0
mp_region_cfg_1_rd_A	335615710	2719	0	0
mp_region_cfg_2_rd_A	335615710	2955	0	0
mp_region_cfg_3_rd_A	335615710	2907	0	0
mp_region_cfg_4_rd_A	335615710	2696	0	0
mp_region_cfg_5_rd_A	335615710	2718	0	0
mp_region_cfg_6_rd_A	335615710	2955	0	0
mp_region_cfg_7_rd_A	335615710	2711	0	0
phy_alert_cfg_rd_A	335615710	383	0	0
region_cfg_regwen_0_rd_A	335615710	1459	0	0
region_cfg_regwen_1_rd_A	335615710	1620	0	0
region_cfg_regwen_2_rd_A	335615710	1597	0	0
region_cfg_regwen_3_rd_A	335615710	1507	0	0
region_cfg_regwen_4_rd_A	335615710	1605	0	0
region_cfg_regwen_5_rd_A	335615710	1784	0	0
region_cfg_regwen_6_rd_A	335615710	1545	0	0
region_cfg_regwen_7_rd_A	335615710	1558	0	0
scratch_rd_A	335615710	1605	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	4537	0	0
T136	2965	187	0	0
T137	2395	51	0	0
T139	3910	9	0	0
T140	3017	222	0	0
T240	5596	185	0	0
T241	5366	237	0	0
T242	8032	10	0	0
T251	4727	248	0	0
T252	3167	66	0	0
T253	2131	4	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1619	0	0
T138	5670	8	0	0
T259	10407	24	0	0
T260	3419	9	0	0
T261	10060	1	0	0
T271	3185	4	0	0
T303	9762	4	0	0
T304	309824	437	0	0
T305	19135	19	0	0
T306	7380	7	0	0
T307	11233	12	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2751	0	0
T138	5670	28	0	0
T259	10407	35	0	0
T260	3419	22	0	0
T261	10060	9	0	0
T271	3185	3	0	0
T303	9762	9	0	0
T304	309824	462	0	0
T305	19135	11	0	0
T306	7380	8	0	0
T307	11233	27	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2749	0	0
T138	5670	19	0	0
T259	10407	29	0	0
T260	3419	6	0	0
T261	10060	21	0	0
T271	3185	1	0	0
T303	9762	28	0	0
T304	309824	436	0	0
T305	19135	23	0	0
T306	7380	39	0	0
T307	11233	40	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	3030	0	0
T138	5670	8	0	0
T259	10407	17	0	0
T260	3419	21	0	0
T261	10060	51	0	0
T271	3185	9	0	0
T304	309824	462	0	0
T305	19135	34	0	0
T306	7380	34	0	0
T307	11233	23	0	0
T308	17500	41	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2908	0	0
T138	5670	12	0	0
T259	10407	20	0	0
T260	3419	4	0	0
T261	10060	3	0	0
T271	3185	1	0	0
T303	9762	24	0	0
T304	309824	495	0	0
T305	19135	18	0	0
T306	7380	57	0	0
T307	11233	39	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2922	0	0
T138	5670	7	0	0
T259	10407	26	0	0
T261	10060	48	0	0
T271	3185	4	0	0
T303	9762	3	0	0
T304	309824	416	0	0
T305	19135	36	0	0
T306	7380	40	0	0
T307	11233	6	0	0
T308	17500	19	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2814	0	0
T138	5670	4	0	0
T259	10407	7	0	0
T260	3419	38	0	0
T261	10060	35	0	0
T271	3185	2	0	0
T303	9762	25	0	0
T304	309824	433	0	0
T305	19135	9	0	0
T306	7380	7	0	0
T307	11233	5	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2742	0	0
T138	5670	3	0	0
T259	10407	15	0	0
T260	3419	31	0	0
T271	3185	1	0	0
T303	9762	19	0	0
T304	309824	403	0	0
T305	19135	21	0	0
T306	7380	22	0	0
T307	11233	32	0	0
T308	17500	28	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2889	0	0
T138	5670	18	0	0
T259	10407	33	0	0
T260	3419	35	0	0
T271	3185	1	0	0
T303	9762	21	0	0
T304	309824	422	0	0
T305	19135	9	0	0
T306	7380	37	0	0
T307	11233	31	0	0
T308	17500	24	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2783	0	0
T138	5670	14	0	0
T259	10407	10	0	0
T260	3419	4	0	0
T261	10060	23	0	0
T271	3185	2	0	0
T303	9762	11	0	0
T304	309824	447	0	0
T305	19135	38	0	0
T306	7380	11	0	0
T307	11233	27	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2846	0	0
T138	5670	35	0	0
T259	10407	26	0	0
T260	3419	40	0	0
T261	10060	39	0	0
T271	3185	8	0	0
T303	9762	20	0	0
T304	309824	427	0	0
T305	19135	31	0	0
T306	7380	51	0	0
T308	17500	27	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1721	0	0
T138	5670	6	0	0
T259	10407	13	0	0
T260	3419	9	0	0
T261	10060	7	0	0
T303	9762	12	0	0
T304	309824	451	0	0
T305	19135	13	0	0
T306	7380	5	0	0
T307	11233	6	0	0
T308	17500	26	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1649	0	0
T138	5670	8	0	0
T259	10407	16	0	0
T260	3419	4	0	0
T261	10060	5	0	0
T271	3185	6	0	0
T303	9762	30	0	0
T304	309824	486	0	0
T305	19135	26	0	0
T306	7380	8	0	0
T307	11233	11	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1563	0	0
T138	5670	13	0	0
T259	10407	23	0	0
T260	3419	9	0	0
T261	10060	16	0	0
T271	3185	1	0	0
T303	9762	14	0	0
T304	309824	415	0	0
T305	19135	36	0	0
T306	7380	6	0	0
T307	11233	27	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1801	0	0
T138	5670	8	0	0
T259	10407	13	0	0
T260	3419	4	0	0
T261	10060	30	0	0
T271	3185	5	0	0
T303	9762	16	0	0
T304	309824	489	0	0
T305	19135	11	0	0
T306	7380	10	0	0
T307	11233	28	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1640	0	0
T138	5670	5	0	0
T259	10407	32	0	0
T260	3419	3	0	0
T261	10060	47	0	0
T303	9762	41	0	0
T304	309824	453	0	0
T305	19135	31	0	0
T306	7380	11	0	0
T307	11233	5	0	0
T308	17500	24	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1720	0	0
T138	5670	9	0	0
T259	10407	29	0	0
T260	3419	2	0	0
T271	3185	6	0	0
T303	9762	17	0	0
T304	309824	451	0	0
T305	19135	49	0	0
T306	7380	4	0	0
T307	11233	5	0	0
T308	17500	14	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1744	0	0
T138	5670	1	0	0
T259	10407	31	0	0
T260	3419	5	0	0
T261	10060	55	0	0
T271	3185	8	0	0
T303	9762	16	0	0
T304	309824	453	0	0
T305	19135	24	0	0
T306	7380	15	0	0
T307	11233	50	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1563	0	0
T138	5670	9	0	0
T260	3419	2	0	0
T261	10060	6	0	0
T271	3185	5	0	0
T303	9762	16	0	0
T304	309824	454	0	0
T305	19135	7	0	0
T306	7380	9	0	0
T307	11233	34	0	0
T308	17500	23	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1627	0	0
T138	5670	3	0	0
T259	10407	29	0	0
T260	3419	3	0	0
T261	10060	9	0	0
T271	3185	7	0	0
T303	9762	11	0	0
T304	309824	439	0	0
T305	19135	20	0	0
T306	7380	11	0	0
T307	11233	26	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1759	0	0
T138	5670	7	0	0
T259	10407	39	0	0
T260	3419	3	0	0
T261	10060	30	0	0
T271	3185	9	0	0
T303	9762	18	0	0
T304	309824	472	0	0
T305	19135	3	0	0
T306	7380	8	0	0
T307	11233	33	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2862	0	0
T138	5670	5	0	0
T259	10407	3	0	0
T260	3419	6	0	0
T261	10060	18	0	0
T271	3185	8	0	0
T303	9762	28	0	0
T304	309824	452	0	0
T305	19135	6	0	0
T306	7380	31	0	0
T307	11233	17	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1569	0	0
T138	5670	10	0	0
T259	10407	40	0	0
T260	3419	2	0	0
T261	10060	44	0	0
T271	3185	1	0	0
T303	9762	11	0	0
T304	309824	422	0	0
T305	19135	19	0	0
T306	7380	10	0	0
T307	11233	38	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2905	0	0
T138	5670	11	0	0
T259	10407	1	0	0
T260	3419	38	0	0
T261	10060	35	0	0
T303	9762	9	0	0
T304	309824	379	0	0
T305	19135	52	0	0
T306	7380	30	0	0
T307	11233	62	0	0
T308	17500	24	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	3017	0	0
T138	5670	22	0	0
T259	10407	6	0	0
T260	3419	19	0	0
T261	10060	9	0	0
T271	3185	1	0	0
T303	9762	17	0	0
T304	309824	447	0	0
T305	19135	32	0	0
T306	7380	10	0	0
T307	11233	14	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1555	0	0
T259	10407	2	0	0
T260	3419	7	0	0
T261	10060	22	0	0
T271	3185	2	0	0
T304	309824	461	0	0
T305	19135	9	0	0
T306	7380	14	0	0
T307	11233	34	0	0
T308	17500	39	0	0
T309	9187	5	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1655	0	0
T138	5670	4	0	0
T260	3419	3	0	0
T261	10060	31	0	0
T303	9762	19	0	0
T304	309824	406	0	0
T305	19135	18	0	0
T306	7380	1	0	0
T308	17500	45	0	0
T309	9187	11	0	0
T310	9189	8	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2899	0	0
T138	5670	28	0	0
T259	10407	9	0	0
T260	3419	41	0	0
T261	10060	19	0	0
T271	3185	2	0	0
T303	9762	16	0	0
T304	309824	445	0	0
T305	19135	15	0	0
T306	7380	50	0	0
T308	17500	20	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2770	0	0
T138	5670	10	0	0
T259	10407	14	0	0
T260	3419	3	0	0
T261	10060	4	0	0
T271	3185	1	0	0
T303	9762	12	0	0
T304	309824	486	0	0
T305	19135	29	0	0
T306	7380	27	0	0
T307	11233	20	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2836	0	0
T138	5670	26	0	0
T259	10407	13	0	0
T261	10060	10	0	0
T271	3185	5	0	0
T303	9762	38	0	0
T304	309824	464	0	0
T305	19135	23	0	0
T306	7380	57	0	0
T307	11233	27	0	0
T308	17500	32	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	3158	0	0
T138	5670	28	0	0
T259	10407	21	0	0
T260	3419	29	0	0
T261	10060	3	0	0
T271	3185	4	0	0
T303	9762	5	0	0
T304	309824	470	0	0
T305	19135	16	0	0
T306	7380	35	0	0
T307	11233	41	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2664	0	0
T138	5670	30	0	0
T259	10407	28	0	0
T260	3419	27	0	0
T261	10060	37	0	0
T271	3185	4	0	0
T303	9762	13	0	0
T304	309824	428	0	0
T305	19135	25	0	0
T307	11233	10	0	0
T308	17500	41	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2612	0	0
T138	5670	1	0	0
T259	10407	35	0	0
T260	3419	30	0	0
T261	10060	23	0	0
T271	3185	8	0	0
T303	9762	19	0	0
T304	309824	401	0	0
T305	19135	36	0	0
T306	7380	29	0	0
T307	11233	27	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2856	0	0
T138	5670	2	0	0
T259	10407	11	0	0
T260	3419	9	0	0
T261	10060	7	0	0
T303	9762	5	0	0
T304	309824	437	0	0
T305	19135	39	0	0
T306	7380	43	0	0
T307	11233	18	0	0
T308	17500	30	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2601	0	0
T138	5670	33	0	0
T260	3419	32	0	0
T261	10060	10	0	0
T303	9762	10	0	0
T304	309824	440	0	0
T305	19135	23	0	0
T306	7380	46	0	0
T307	11233	30	0	0
T308	17500	47	0	0
T309	9187	17	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	3056	0	0
T138	5670	18	0	0
T259	10407	2	0	0
T260	3419	27	0	0
T261	10060	25	0	0
T271	3185	9	0	0
T304	309824	458	0	0
T305	19135	18	0	0
T306	7380	6	0	0
T307	11233	5	0	0
T308	17500	37	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2386	0	0
T138	5670	37	0	0
T259	10407	3	0	0
T260	3419	34	0	0
T261	10060	19	0	0
T271	3185	1	0	0
T303	9762	20	0	0
T304	309824	474	0	0
T305	19135	18	0	0
T306	7380	16	0	0
T308	17500	47	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1638	0	0
T138	5670	8	0	0
T259	10407	21	0	0
T260	3419	1	0	0
T271	3185	6	0	0
T303	9762	20	0	0
T304	309824	449	0	0
T305	19135	26	0	0
T306	7380	11	0	0
T307	11233	39	0	0
T308	17500	27	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1697	0	0
T138	5670	9	0	0
T259	10407	43	0	0
T260	3419	8	0	0
T261	10060	10	0	0
T271	3185	6	0	0
T303	9762	5	0	0
T304	309824	402	0	0
T305	19135	27	0	0
T306	7380	9	0	0
T307	11233	37	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1636	0	0
T138	5670	8	0	0
T259	10407	44	0	0
T260	3419	3	0	0
T261	10060	5	0	0
T271	3185	4	0	0
T303	9762	21	0	0
T304	309824	452	0	0
T305	19135	10	0	0
T306	7380	5	0	0
T307	11233	20	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1694	0	0
T138	5670	3	0	0
T259	10407	21	0	0
T260	3419	2	0	0
T261	10060	6	0	0
T303	9762	1	0	0
T304	309824	477	0	0
T305	19135	14	0	0
T306	7380	9	0	0
T307	11233	42	0	0
T308	17500	37	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1638	0	0
T138	5670	10	0	0
T259	10407	46	0	0
T260	3419	7	0	0
T261	10060	10	0	0
T271	3185	7	0	0
T303	9762	16	0	0
T304	309824	450	0	0
T305	19135	28	0	0
T306	7380	6	0	0
T307	11233	35	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1555	0	0
T138	5670	5	0	0
T259	10407	12	0	0
T260	3419	3	0	0
T261	10060	2	0	0
T271	3185	7	0	0
T303	9762	9	0	0
T304	309824	420	0	0
T305	19135	15	0	0
T306	7380	15	0	0
T307	11233	10	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1653	0	0
T138	5670	13	0	0
T259	10407	44	0	0
T260	3419	5	0	0
T261	10060	28	0	0
T271	3185	2	0	0
T303	9762	8	0	0
T304	309824	504	0	0
T305	19135	1	0	0
T306	7380	9	0	0
T307	11233	35	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1619	0	0
T138	5670	7	0	0
T259	10407	16	0	0
T260	3419	10	0	0
T261	10060	9	0	0
T271	3185	4	0	0
T303	9762	10	0	0
T304	309824	424	0	0
T305	19135	39	0	0
T306	7380	3	0	0
T307	11233	19	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1611	0	0
T138	5670	9	0	0
T259	10407	43	0	0
T260	3419	9	0	0
T261	10060	5	0	0
T271	3185	2	0	0
T303	9762	4	0	0
T304	309824	445	0	0
T305	19135	57	0	0
T306	7380	12	0	0
T307	11233	14	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1720	0	0
T138	5670	8	0	0
T259	10407	38	0	0
T260	3419	2	0	0
T261	10060	11	0	0
T271	3185	7	0	0
T304	309824	454	0	0
T305	19135	40	0	0
T306	7380	10	0	0
T307	11233	24	0	0
T308	17500	48	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2998	0	0
T138	5670	7	0	0
T259	10407	43	0	0
T260	3419	5	0	0
T261	10060	6	0	0
T303	9762	9	0	0
T304	309824	432	0	0
T305	19135	20	0	0
T306	7380	6	0	0
T307	11233	13	0	0
T308	17500	19	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1685	0	0
T138	5670	8	0	0
T259	10407	37	0	0
T260	3419	6	0	0
T261	10060	28	0	0
T271	3185	2	0	0
T303	9762	7	0	0
T304	309824	453	0	0
T305	19135	23	0	0
T306	7380	7	0	0
T307	11233	28	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2710	0	0
T138	5670	19	0	0
T259	10407	34	0	0
T260	3419	2	0	0
T261	10060	14	0	0
T271	3185	7	0	0
T304	309824	430	0	0
T305	19135	21	0	0
T306	7380	81	0	0
T307	11233	31	0	0
T308	17500	19	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2951	0	0
T138	5670	6	0	0
T259	10407	28	0	0
T260	3419	22	0	0
T303	9762	4	0	0
T304	309824	486	0	0
T305	19135	17	0	0
T306	7380	33	0	0
T307	11233	7	0	0
T308	17500	7	0	0
T309	9187	31	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1768	0	0
T138	5670	4	0	0
T259	10407	15	0	0
T260	3419	7	0	0
T261	10060	19	0	0
T271	3185	8	0	0
T303	9762	9	0	0
T304	309824	430	0	0
T305	19135	46	0	0
T306	7380	9	0	0
T307	11233	31	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1685	0	0
T138	5670	8	0	0
T259	10407	2	0	0
T260	3419	2	0	0
T261	10060	7	0	0
T271	3185	9	0	0
T303	9762	18	0	0
T304	309824	437	0	0
T305	19135	17	0	0
T306	7380	7	0	0
T307	11233	37	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1718	0	0
T138	5670	17	0	0
T259	10407	26	0	0
T260	3419	1	0	0
T261	10060	27	0	0
T303	9762	15	0	0
T304	309824	498	0	0
T305	19135	11	0	0
T306	7380	5	0	0
T307	11233	35	0	0
T308	17500	42	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2601	0	0
T138	5670	32	0	0
T259	10407	28	0	0
T260	3419	7	0	0
T261	10060	21	0	0
T271	3185	2	0	0
T303	9762	18	0	0
T304	309824	451	0	0
T305	19135	39	0	0
T306	7380	9	0	0
T307	11233	19	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1646	0	0
T138	5670	12	0	0
T259	10407	34	0	0
T260	3419	2	0	0
T261	10060	19	0	0
T271	3185	4	0	0
T303	9762	5	0	0
T304	309824	426	0	0
T305	19135	9	0	0
T306	7380	8	0	0
T307	11233	30	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1790	0	0
T138	5670	6	0	0
T259	10407	15	0	0
T260	3419	6	0	0
T261	10060	18	0	0
T304	309824	472	0	0
T305	19135	25	0	0
T306	7380	10	0	0
T307	11233	23	0	0
T308	17500	19	0	0
T309	9187	4	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1626	0	0
T138	5670	12	0	0
T259	10407	11	0	0
T260	3419	1	0	0
T261	10060	15	0	0
T271	3185	3	0	0
T303	9762	10	0	0
T304	309824	455	0	0
T305	19135	55	0	0
T306	7380	12	0	0
T307	11233	37	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1990	0	0
T138	5670	6	0	0
T259	10407	39	0	0
T260	3419	14	0	0
T261	10060	48	0	0
T271	3185	6	0	0
T303	9762	17	0	0
T304	309824	508	0	0
T305	19135	32	0	0
T306	7380	13	0	0
T307	11233	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2448	0	0
T138	5670	10	0	0
T259	10407	9	0	0
T260	3419	8	0	0
T271	3185	9	0	0
T303	9762	17	0	0
T304	309824	454	0	0
T305	19135	28	0	0
T306	7380	5	0	0
T307	11233	25	0	0
T308	17500	33	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1867	0	0
T138	5670	15	0	0
T259	10407	3	0	0
T260	3419	9	0	0
T261	10060	6	0	0
T271	3185	10	0	0
T303	9762	6	0	0
T304	309824	434	0	0
T305	19135	12	0	0
T306	7380	5	0	0
T307	11233	50	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1859	0	0
T138	5670	8	0	0
T260	3419	6	0	0
T261	10060	23	0	0
T271	3185	5	0	0
T303	9762	29	0	0
T304	309824	474	0	0
T305	19135	17	0	0
T306	7380	9	0	0
T307	11233	30	0	0
T308	17500	30	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2087	0	0
T138	5670	8	0	0
T259	10407	33	0	0
T260	3419	6	0	0
T261	10060	9	0	0
T303	9762	6	0	0
T304	309824	500	0	0
T305	19135	36	0	0
T306	7380	19	0	0
T307	11233	17	0	0
T308	17500	20	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1939	0	0
T138	5670	8	0	0
T259	10407	49	0	0
T260	3419	16	0	0
T261	10060	8	0	0
T271	3185	3	0	0
T303	9762	1	0	0
T304	309824	470	0	0
T305	19135	35	0	0
T306	7380	10	0	0
T307	11233	19	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1949	0	0
T138	5670	24	0	0
T259	10407	12	0	0
T260	3419	8	0	0
T261	10060	44	0	0
T271	3185	2	0	0
T303	9762	14	0	0
T304	309824	477	0	0
T305	19135	8	0	0
T306	7380	17	0	0
T307	11233	32	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1802	0	0
T138	5670	19	0	0
T259	10407	22	0	0
T260	3419	2	0	0
T261	10060	13	0	0
T271	3185	1	0	0
T303	9762	8	0	0
T304	309824	394	0	0
T305	19135	34	0	0
T306	7380	36	0	0
T307	11233	51	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1791	0	0
T138	5670	17	0	0
T259	10407	26	0	0
T261	10060	18	0	0
T271	3185	1	0	0
T303	9762	3	0	0
T304	309824	433	0	0
T305	19135	9	0	0
T306	7380	3	0	0
T307	11233	12	0	0
T308	17500	43	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1823	0	0
T138	5670	13	0	0
T259	10407	26	0	0
T260	3419	2	0	0
T261	10060	26	0	0
T271	3185	3	0	0
T303	9762	32	0	0
T304	309824	455	0	0
T305	19135	10	0	0
T306	7380	24	0	0
T307	11233	17	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	3036	0	0
T138	5670	5	0	0
T259	10407	23	0	0
T260	3419	17	0	0
T271	3185	7	0	0
T304	309824	484	0	0
T305	19135	19	0	0
T306	7380	50	0	0
T307	11233	10	0	0
T308	17500	39	0	0
T309	9187	35	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2719	0	0
T138	5670	13	0	0
T259	10407	31	0	0
T260	3419	2	0	0
T261	10060	6	0	0
T271	3185	8	0	0
T303	9762	6	0	0
T304	309824	401	0	0
T305	19135	26	0	0
T306	7380	15	0	0
T307	11233	61	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2955	0	0
T138	5670	25	0	0
T259	10407	31	0	0
T260	3419	3	0	0
T261	10060	29	0	0
T303	9762	10	0	0
T304	309824	478	0	0
T305	19135	6	0	0
T306	7380	55	0	0
T307	11233	26	0	0
T308	17500	27	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2907	0	0
T138	5670	8	0	0
T259	10407	34	0	0
T260	3419	6	0	0
T261	10060	6	0	0
T271	3185	6	0	0
T303	9762	2	0	0
T304	309824	414	0	0
T305	19135	34	0	0
T306	7380	41	0	0
T307	11233	49	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2696	0	0
T138	5670	27	0	0
T259	10407	26	0	0
T260	3419	4	0	0
T261	10060	8	0	0
T271	3185	8	0	0
T303	9762	19	0	0
T304	309824	439	0	0
T305	19135	26	0	0
T306	7380	23	0	0
T307	11233	3	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2718	0	0
T138	5670	4	0	0
T259	10407	18	0	0
T260	3419	1	0	0
T261	10060	1	0	0
T271	3185	6	0	0
T304	309824	501	0	0
T305	19135	7	0	0
T306	7380	71	0	0
T308	17500	23	0	0
T309	9187	27	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2955	0	0
T138	5670	15	0	0
T259	10407	35	0	0
T260	3419	24	0	0
T261	10060	26	0	0
T271	3185	1	0	0
T303	9762	11	0	0
T304	309824	465	0	0
T305	19135	33	0	0
T306	7380	15	0	0
T307	11233	32	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	2711	0	0
T138	5670	32	0	0
T259	10407	30	0	0
T260	3419	29	0	0
T261	10060	38	0	0
T271	3185	1	0	0
T303	9762	3	0	0
T304	309824	423	0	0
T305	19135	9	0	0
T306	7380	52	0	0
T307	11233	16	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	383	0	0
T138	5670	6	0	0
T259	10407	30	0	0
T261	10060	29	0	0
T271	3185	7	0	0
T303	9762	11	0	0
T305	19135	29	0	0
T307	11233	69	0	0
T308	17500	20	0	0
T309	9187	17	0	0
T310	9189	1	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1459	0	0
T138	5670	9	0	0
T259	10407	35	0	0
T261	10060	18	0	0
T271	3185	6	0	0
T303	9762	5	0	0
T304	309824	376	0	0
T305	19135	33	0	0
T306	7380	3	0	0
T307	11233	14	0	0
T308	17500	4	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1620	0	0
T138	5670	5	0	0
T259	10407	41	0	0
T261	10060	15	0	0
T271	3185	2	0	0
T304	309824	491	0	0
T305	19135	26	0	0
T306	7380	5	0	0
T307	11233	21	0	0
T308	17500	13	0	0
T309	9187	8	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1597	0	0
T138	5670	1	0	0
T259	10407	23	0	0
T260	3419	2	0	0
T261	10060	48	0	0
T271	3185	8	0	0
T303	9762	23	0	0
T304	309824	462	0	0
T305	19135	25	0	0
T306	7380	10	0	0
T307	11233	35	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1507	0	0
T138	5670	3	0	0
T259	10407	18	0	0
T260	3419	5	0	0
T261	10060	13	0	0
T271	3185	10	0	0
T303	9762	5	0	0
T304	309824	418	0	0
T305	19135	22	0	0
T306	7380	7	0	0
T307	11233	3	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1605	0	0
T138	5670	9	0	0
T259	10407	10	0	0
T260	3419	1	0	0
T261	10060	13	0	0
T304	309824	477	0	0
T305	19135	25	0	0
T306	7380	9	0	0
T307	11233	18	0	0
T308	17500	33	0	0
T309	9187	14	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1784	0	0
T138	5670	12	0	0
T259	10407	28	0	0
T260	3419	9	0	0
T261	10060	4	0	0
T271	3185	9	0	0
T303	9762	7	0	0
T304	309824	477	0	0
T305	19135	51	0	0
T306	7380	1	0	0
T307	11233	48	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1545	0	0
T138	5670	13	0	0
T259	10407	14	0	0
T261	10060	2	0	0
T271	3185	6	0	0
T303	9762	26	0	0
T304	309824	431	0	0
T305	19135	59	0	0
T306	7380	4	0	0
T307	11233	2	0	0
T308	17500	19	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1558	0	0
T138	5670	2	0	0
T259	10407	4	0	0
T260	3419	9	0	0
T261	10060	10	0	0
T271	3185	3	0	0
T303	9762	14	0	0
T304	309824	416	0	0
T305	19135	4	0	0
T306	7380	6	0	0
T307	11233	15	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	335615710	1605	0	0
T138	5670	1	0	0
T259	10407	20	0	0
T303	9762	2	0	0
T304	309824	393	0	0
T305	19135	40	0	0
T306	7380	2	0	0
T307	11233	19	0	0
T308	17500	20	0	0
T309	9187	16	0	0
T310	9189	1	0	0