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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.87 95.23 93.61 98.31 91.84 97.12 96.89 98.09


Total test records in report: 1241
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html

T299 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.929042003 Aug 25 02:33:40 PM UTC 24 Aug 25 02:34:09 PM UTC 24 15159200 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.2978784553 Aug 25 02:30:30 PM UTC 24 Aug 25 02:34:11 PM UTC 24 147015300 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.1345348794 Aug 25 02:33:15 PM UTC 24 Aug 25 02:34:12 PM UTC 24 30811900 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.2243636998 Aug 25 02:22:36 PM UTC 24 Aug 25 02:34:12 PM UTC 24 4499538900 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1446916067 Aug 25 02:33:30 PM UTC 24 Aug 25 02:34:12 PM UTC 24 36385300 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.222147202 Aug 25 02:29:12 PM UTC 24 Aug 25 02:34:16 PM UTC 24 57172065000 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1955565586 Aug 25 02:33:19 PM UTC 24 Aug 25 02:34:22 PM UTC 24 103697800 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.765635018 Aug 25 02:31:11 PM UTC 24 Aug 25 02:34:25 PM UTC 24 2414216900 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1199243622 Aug 25 02:34:00 PM UTC 24 Aug 25 02:34:26 PM UTC 24 30599400 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.865519299 Aug 25 02:30:30 PM UTC 24 Aug 25 02:34:36 PM UTC 24 10597020300 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.170227148 Aug 25 02:17:14 PM UTC 24 Aug 25 02:34:42 PM UTC 24 60130024300 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.3107589073 Aug 25 02:34:13 PM UTC 24 Aug 25 02:34:49 PM UTC 24 472844200 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2330843458 Aug 25 02:30:42 PM UTC 24 Aug 25 02:35:00 PM UTC 24 9931665100 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3941051629 Aug 25 02:33:33 PM UTC 24 Aug 25 02:35:22 PM UTC 24 4094764700 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.2033732795 Aug 25 02:30:57 PM UTC 24 Aug 25 02:35:24 PM UTC 24 2141096100 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.3454279834 Aug 25 02:31:14 PM UTC 24 Aug 25 02:35:41 PM UTC 24 1757795700 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.245604229 Aug 25 02:28:43 PM UTC 24 Aug 25 02:35:47 PM UTC 24 25538329900 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.1822421038 Aug 25 02:31:11 PM UTC 24 Aug 25 02:35:52 PM UTC 24 6453867600 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.3807376078 Aug 25 02:34:10 PM UTC 24 Aug 25 02:36:01 PM UTC 24 3371064800 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1251421258 Aug 25 02:33:51 PM UTC 24 Aug 25 02:36:24 PM UTC 24 10015179300 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.1191320997 Aug 25 02:34:02 PM UTC 24 Aug 25 02:36:27 PM UTC 24 23334100 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.2625883523 Aug 25 02:34:25 PM UTC 24 Aug 25 02:36:32 PM UTC 24 3867177000 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.267752879 Aug 25 02:32:44 PM UTC 24 Aug 25 02:36:35 PM UTC 24 2126202500 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2918180495 Aug 25 02:24:02 PM UTC 24 Aug 25 02:36:39 PM UTC 24 4084951200 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3076969315 Aug 25 02:32:17 PM UTC 24 Aug 25 02:36:45 PM UTC 24 23340314000 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.98560194 Aug 25 02:36:25 PM UTC 24 Aug 25 02:36:51 PM UTC 24 80237600 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.1358692007 Aug 25 02:34:38 PM UTC 24 Aug 25 02:36:57 PM UTC 24 453799300 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2099816020 Aug 25 02:26:31 PM UTC 24 Aug 25 02:37:11 PM UTC 24 2130583800 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1908826051 Aug 25 02:21:14 PM UTC 24 Aug 25 02:37:18 PM UTC 24 3088817500 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1919769974 Aug 25 02:36:53 PM UTC 24 Aug 25 02:37:19 PM UTC 24 31269900 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.218299516 Aug 25 02:36:28 PM UTC 24 Aug 25 02:37:20 PM UTC 24 68406000 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2472041084 Aug 25 02:36:40 PM UTC 24 Aug 25 02:37:20 PM UTC 24 44866000 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.337151070 Aug 25 02:36:58 PM UTC 24 Aug 25 02:37:22 PM UTC 24 26600900 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1153073253 Aug 25 02:35:48 PM UTC 24 Aug 25 02:37:23 PM UTC 24 4332401900 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.2384500476 Aug 25 02:36:33 PM UTC 24 Aug 25 02:37:26 PM UTC 24 77252700 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.3078712404 Aug 25 02:34:50 PM UTC 24 Aug 25 02:37:37 PM UTC 24 690990900 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.3474602351 Aug 25 02:36:35 PM UTC 24 Aug 25 02:37:38 PM UTC 24 124534300 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1627279118 Aug 25 02:37:12 PM UTC 24 Aug 25 02:37:40 PM UTC 24 26024000 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.4056435404 Aug 25 02:37:20 PM UTC 24 Aug 25 02:37:45 PM UTC 24 73597900 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2730057562 Aug 25 02:16:54 PM UTC 24 Aug 25 02:37:50 PM UTC 24 1485317200 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.403039260 Aug 25 02:21:26 PM UTC 24 Aug 25 02:38:08 PM UTC 24 2038162200 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3343464119 Aug 25 02:35:23 PM UTC 24 Aug 25 02:38:10 PM UTC 24 1476986500 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2682311693 Aug 25 02:34:13 PM UTC 24 Aug 25 02:38:16 PM UTC 24 407202000 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.1895111586 Aug 25 02:37:41 PM UTC 24 Aug 25 02:38:16 PM UTC 24 1008961400 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1142083120 Aug 25 02:37:23 PM UTC 24 Aug 25 02:38:24 PM UTC 24 831072800 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.400792131 Aug 25 02:37:19 PM UTC 24 Aug 25 02:38:31 PM UTC 24 10117472800 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.3556262522 Aug 25 02:36:45 PM UTC 24 Aug 25 02:38:46 PM UTC 24 7265280500 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.4074493905 Aug 25 02:35:01 PM UTC 24 Aug 25 02:38:47 PM UTC 24 7479587800 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.2077612953 Aug 25 02:34:08 PM UTC 24 Aug 25 02:38:48 PM UTC 24 57766300 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3243257297 Aug 25 02:32:06 PM UTC 24 Aug 25 02:38:54 PM UTC 24 12576882700 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.394963033 Aug 25 02:21:35 PM UTC 24 Aug 25 02:39:01 PM UTC 24 120152578300 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.427277281 Aug 25 02:12:41 PM UTC 24 Aug 25 02:39:06 PM UTC 24 99596451500 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2900507742 Aug 25 02:28:39 PM UTC 24 Aug 25 02:39:13 PM UTC 24 4135269500 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1821120791 Aug 25 02:35:24 PM UTC 24 Aug 25 02:39:14 PM UTC 24 1469186500 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.798357450 Aug 25 02:13:21 PM UTC 24 Aug 25 02:39:23 PM UTC 24 2599386600 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.3380053940 Aug 25 02:34:26 PM UTC 24 Aug 25 02:39:26 PM UTC 24 19085481200 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.3215555131 Aug 25 02:38:08 PM UTC 24 Aug 25 02:39:35 PM UTC 24 1859748900 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.779272316 Aug 25 02:39:27 PM UTC 24 Aug 25 02:40:03 PM UTC 24 15801500 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.75270967 Aug 25 02:39:24 PM UTC 24 Aug 25 02:40:15 PM UTC 24 47747100 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.2438331329 Aug 25 02:27:35 PM UTC 24 Aug 25 02:40:20 PM UTC 24 4441598100 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.380436322 Aug 25 02:39:56 PM UTC 24 Aug 25 02:40:22 PM UTC 24 45610900 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2461940438 Aug 25 02:40:00 PM UTC 24 Aug 25 02:40:24 PM UTC 24 16172400 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.4060964325 Aug 25 02:40:02 PM UTC 24 Aug 25 02:40:26 PM UTC 24 28785700 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3267661910 Aug 25 02:39:27 PM UTC 24 Aug 25 02:40:29 PM UTC 24 72331000 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4165356875 Aug 25 02:36:02 PM UTC 24 Aug 25 02:40:38 PM UTC 24 18059085400 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1209775932 Aug 25 02:40:16 PM UTC 24 Aug 25 02:40:41 PM UTC 24 62860500 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.2680077756 Aug 25 02:37:39 PM UTC 24 Aug 25 02:40:52 PM UTC 24 38033100 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.104162614 Aug 25 02:38:16 PM UTC 24 Aug 25 02:40:54 PM UTC 24 557369500 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2719924319 Aug 25 02:37:21 PM UTC 24 Aug 25 02:40:57 PM UTC 24 25832900 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.2241729060 Aug 25 02:38:54 PM UTC 24 Aug 25 02:40:59 PM UTC 24 10299974400 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2573848286 Aug 25 02:39:35 PM UTC 24 Aug 25 02:41:03 PM UTC 24 504752600 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1776195075 Aug 25 02:12:12 PM UTC 24 Aug 25 02:41:14 PM UTC 24 876952600 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.498780778 Aug 25 02:38:11 PM UTC 24 Aug 25 02:42:49 PM UTC 24 4726797400 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1366377559 Aug 25 02:30:46 PM UTC 24 Aug 25 02:41:17 PM UTC 24 3804087900 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1582682805 Aug 25 02:38:25 PM UTC 24 Aug 25 02:41:25 PM UTC 24 1431445700 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.2727284182 Aug 25 02:35:42 PM UTC 24 Aug 25 02:41:27 PM UTC 24 27349091700 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.212362011 Aug 25 02:40:53 PM UTC 24 Aug 25 02:41:31 PM UTC 24 116240000 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2641729770 Aug 25 02:30:29 PM UTC 24 Aug 25 02:41:38 PM UTC 24 1741089200 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.653070641 Aug 25 02:40:04 PM UTC 24 Aug 25 02:41:39 PM UTC 24 10037011800 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3566754272 Aug 25 02:38:47 PM UTC 24 Aug 25 02:41:39 PM UTC 24 583753200 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2847262962 Aug 25 02:20:55 PM UTC 24 Aug 25 02:41:50 PM UTC 24 70133178900 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.2721519991 Aug 25 02:40:26 PM UTC 24 Aug 25 02:42:16 PM UTC 24 7553157700 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.620244347 Aug 25 02:34:13 PM UTC 24 Aug 25 02:42:31 PM UTC 24 45218711400 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.528975401 Aug 25 02:38:32 PM UTC 24 Aug 25 02:42:36 PM UTC 24 5944835900 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2673039605 Aug 25 02:35:53 PM UTC 24 Aug 25 02:42:42 PM UTC 24 15183259900 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.517011363 Aug 25 02:42:17 PM UTC 24 Aug 25 02:42:47 PM UTC 24 19010400 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.2559808514 Aug 25 02:41:00 PM UTC 24 Aug 25 02:42:52 PM UTC 24 4041070200 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.760028100 Aug 25 02:39:14 PM UTC 24 Aug 25 02:42:53 PM UTC 24 8229231000 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.436701912 Aug 25 02:38:49 PM UTC 24 Aug 25 02:42:55 PM UTC 24 6438908400 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.2922877395 Aug 25 02:42:17 PM UTC 24 Aug 25 02:43:04 PM UTC 24 91686100 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4211103756 Aug 25 02:38:48 PM UTC 24 Aug 25 02:43:11 PM UTC 24 5805021700 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.1445096993 Aug 25 02:42:49 PM UTC 24 Aug 25 02:43:16 PM UTC 24 155609300 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.3030834901 Aug 25 02:42:54 PM UTC 24 Aug 25 02:43:19 PM UTC 24 16689400 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1525396767 Aug 25 02:42:54 PM UTC 24 Aug 25 02:43:19 PM UTC 24 34360500 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3942137627 Aug 25 02:42:43 PM UTC 24 Aug 25 02:43:20 PM UTC 24 13901500 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.2887069157 Aug 25 02:34:43 PM UTC 24 Aug 25 02:43:21 PM UTC 24 3798712900 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.2593908709 Aug 25 02:48:02 PM UTC 24 Aug 25 02:48:28 PM UTC 24 56313400 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.1885852962 Aug 25 02:41:40 PM UTC 24 Aug 25 02:43:22 PM UTC 24 8059928600 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.798674986 Aug 25 02:43:05 PM UTC 24 Aug 25 02:43:31 PM UTC 24 72449000 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.1202212386 Aug 25 02:40:21 PM UTC 24 Aug 25 02:43:42 PM UTC 24 2772089800 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1937352587 Aug 25 02:42:37 PM UTC 24 Aug 25 02:43:45 PM UTC 24 266418500 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.3738296272 Aug 25 02:41:05 PM UTC 24 Aug 25 02:43:45 PM UTC 24 1227964600 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1085872370 Aug 25 02:40:38 PM UTC 24 Aug 25 02:43:50 PM UTC 24 40784400 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2002468017 Aug 25 02:12:19 PM UTC 24 Aug 25 02:43:52 PM UTC 24 776438500 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.739523842 Aug 25 02:41:18 PM UTC 24 Aug 25 02:44:01 PM UTC 24 2384597300 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3569486374 Aug 25 02:37:40 PM UTC 24 Aug 25 02:44:04 PM UTC 24 21380919300 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.1516665323 Aug 25 02:42:47 PM UTC 24 Aug 25 02:44:13 PM UTC 24 702216300 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1770367285 Aug 25 02:43:24 PM UTC 24 Aug 25 02:44:17 PM UTC 24 1880878600 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.991460101 Aug 25 02:41:04 PM UTC 24 Aug 25 02:44:26 PM UTC 24 2162521100 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.2192799409 Aug 25 02:17:44 PM UTC 24 Aug 25 02:44:36 PM UTC 24 686337100 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2995070985 Aug 25 02:41:28 PM UTC 24 Aug 25 02:44:41 PM UTC 24 721117800 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3343604379 Aug 25 02:39:06 PM UTC 24 Aug 25 02:44:49 PM UTC 24 50340704400 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.1215569580 Aug 25 02:26:37 PM UTC 24 Aug 25 02:45:24 PM UTC 24 40125330700 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.4209870165 Aug 25 02:43:46 PM UTC 24 Aug 25 02:45:32 PM UTC 24 4655771500 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2206037628 Aug 25 02:16:30 PM UTC 24 Aug 25 02:45:42 PM UTC 24 663266710600 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.346537525 Aug 25 02:45:25 PM UTC 24 Aug 25 02:45:49 PM UTC 24 58040200 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.2074787307 Aug 25 02:41:25 PM UTC 24 Aug 25 02:45:49 PM UTC 24 1435679600 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3240747181 Aug 25 02:41:40 PM UTC 24 Aug 25 02:45:57 PM UTC 24 19792878900 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.3520447355 Aug 25 02:43:19 PM UTC 24 Aug 25 02:46:03 PM UTC 24 10692660500 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3695265725 Aug 25 02:43:51 PM UTC 24 Aug 25 02:46:15 PM UTC 24 1143423800 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2723435445 Aug 25 02:45:28 PM UTC 24 Aug 25 02:46:21 PM UTC 24 41930100 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3877338075 Aug 25 02:41:32 PM UTC 24 Aug 25 02:46:22 PM UTC 24 1614283100 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2797284886 Aug 25 02:45:58 PM UTC 24 Aug 25 02:46:25 PM UTC 24 45203600 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1349720382 Aug 25 02:40:25 PM UTC 24 Aug 25 02:46:26 PM UTC 24 724961100 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3348755551 Aug 25 02:45:49 PM UTC 24 Aug 25 02:46:27 PM UTC 24 124565200 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1118553457 Aug 25 02:46:04 PM UTC 24 Aug 25 02:46:29 PM UTC 24 47613100 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.2127703021 Aug 25 02:45:33 PM UTC 24 Aug 25 02:46:32 PM UTC 24 32271800 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3589156886 Aug 25 02:42:56 PM UTC 24 Aug 25 02:46:33 PM UTC 24 10019347400 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.3639404407 Aug 25 02:44:36 PM UTC 24 Aug 25 02:46:38 PM UTC 24 10801047600 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.2259982450 Aug 25 02:46:16 PM UTC 24 Aug 25 02:46:41 PM UTC 24 44912900 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.1397278147 Aug 25 02:45:43 PM UTC 24 Aug 25 02:46:48 PM UTC 24 225422300 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.4076894510 Aug 25 02:39:01 PM UTC 24 Aug 25 02:46:50 PM UTC 24 64541510800 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.2294552642 Aug 25 02:46:23 PM UTC 24 Aug 25 02:46:52 PM UTC 24 114453000 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.1525316690 Aug 25 02:44:02 PM UTC 24 Aug 25 02:46:53 PM UTC 24 651876000 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1885508027 Aug 25 02:25:30 PM UTC 24 Aug 25 02:46:55 PM UTC 24 636368100 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1684931882 Aug 25 02:41:40 PM UTC 24 Aug 25 02:46:58 PM UTC 24 31532186200 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.1250986529 Aug 25 02:44:14 PM UTC 24 Aug 25 02:47:08 PM UTC 24 1281924100 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1769354201 Aug 25 02:43:46 PM UTC 24 Aug 25 02:47:11 PM UTC 24 23088569000 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.75579721 Aug 25 02:43:12 PM UTC 24 Aug 25 02:47:18 PM UTC 24 49034100 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3490446146 Aug 25 02:43:22 PM UTC 24 Aug 25 02:47:23 PM UTC 24 154252300 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1015997205 Aug 25 02:46:59 PM UTC 24 Aug 25 02:47:25 PM UTC 24 166887700 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.1440622538 Aug 25 02:45:51 PM UTC 24 Aug 25 02:47:38 PM UTC 24 7273287800 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.1635309130 Aug 25 02:46:25 PM UTC 24 Aug 25 02:47:54 PM UTC 24 54897900 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1636777098 Aug 25 02:41:51 PM UTC 24 Aug 25 02:47:57 PM UTC 24 116465501200 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1225909760 Aug 25 02:44:06 PM UTC 24 Aug 25 02:48:01 PM UTC 24 4206552700 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.2639488359 Aug 25 02:47:24 PM UTC 24 Aug 25 02:48:01 PM UTC 24 104970700 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3042184880 Aug 25 02:47:09 PM UTC 24 Aug 25 02:48:05 PM UTC 24 46480800 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.3447943057 Aug 25 02:38:16 PM UTC 24 Aug 25 02:48:06 PM UTC 24 7510235100 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.1386092445 Aug 25 02:44:18 PM UTC 24 Aug 25 02:48:12 PM UTC 24 1415213400 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2762118532 Aug 25 02:47:39 PM UTC 24 Aug 25 02:48:12 PM UTC 24 136472100 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.1441525553 Aug 25 02:47:12 PM UTC 24 Aug 25 02:48:14 PM UTC 24 44601000 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2278219712 Aug 25 02:47:19 PM UTC 24 Aug 25 02:48:15 PM UTC 24 556674400 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3158518101 Aug 25 02:47:55 PM UTC 24 Aug 25 02:48:19 PM UTC 24 15709300 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.4217360834 Aug 25 02:47:58 PM UTC 24 Aug 25 02:48:24 PM UTC 24 47599000 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1800105729 Aug 25 02:44:26 PM UTC 24 Aug 25 02:48:26 PM UTC 24 1791190600 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.2944403418 Aug 25 02:22:03 PM UTC 24 Aug 25 02:48:39 PM UTC 24 709829000 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.3444433238 Aug 25 02:46:42 PM UTC 24 Aug 25 02:48:48 PM UTC 24 3914382400 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1059359567 Aug 25 02:46:22 PM UTC 24 Aug 25 02:48:51 PM UTC 24 10016751700 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.835491543 Aug 25 02:46:51 PM UTC 24 Aug 25 02:49:21 PM UTC 24 3791937700 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.4231106132 Aug 25 02:47:26 PM UTC 24 Aug 25 02:49:25 PM UTC 24 2411784700 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.3569756403 Aug 25 02:49:13 PM UTC 24 Aug 25 02:49:37 PM UTC 24 41573400 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1905133621 Aug 25 02:48:13 PM UTC 24 Aug 25 02:49:41 PM UTC 24 646391100 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.684427298 Aug 25 02:46:49 PM UTC 24 Aug 25 02:49:45 PM UTC 24 7562640700 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2743599241 Aug 25 02:40:42 PM UTC 24 Aug 25 02:49:46 PM UTC 24 18693938300 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2623807698 Aug 25 02:46:34 PM UTC 24 Aug 25 02:49:53 PM UTC 24 74477400 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1091850753 Aug 25 02:37:22 PM UTC 24 Aug 25 02:50:03 PM UTC 24 2938094900 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.2682906116 Aug 25 02:49:21 PM UTC 24 Aug 25 02:50:13 PM UTC 24 70337000 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.897495639 Aug 25 02:49:47 PM UTC 24 Aug 25 02:50:14 PM UTC 24 33632000 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.2818106246 Aug 25 02:49:27 PM UTC 24 Aug 25 02:50:16 PM UTC 24 84037300 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.2114751538 Aug 25 02:48:25 PM UTC 24 Aug 25 02:50:17 PM UTC 24 6511603000 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.3480036041 Aug 25 02:49:53 PM UTC 24 Aug 25 02:50:17 PM UTC 24 54359600 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2615358878 Aug 25 02:49:42 PM UTC 24 Aug 25 02:50:24 PM UTC 24 12974600 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.308682156 Aug 25 02:46:31 PM UTC 24 Aug 25 02:50:25 PM UTC 24 29967668800 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3418612476 Aug 25 02:50:04 PM UTC 24 Aug 25 02:50:27 PM UTC 24 46000200 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1422930824 Aug 25 02:49:38 PM UTC 24 Aug 25 02:50:36 PM UTC 24 69016800 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.2868545119 Aug 25 02:50:14 PM UTC 24 Aug 25 02:50:40 PM UTC 24 63714600 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3727048428 Aug 25 02:44:50 PM UTC 24 Aug 25 02:50:52 PM UTC 24 114835657100 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.937279550 Aug 25 02:50:06 PM UTC 24 Aug 25 02:50:59 PM UTC 24 10126904000 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.94809873 Aug 25 02:48:28 PM UTC 24 Aug 25 02:51:11 PM UTC 24 1177751300 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.3466779796 Aug 25 02:12:56 PM UTC 24 Aug 25 02:51:12 PM UTC 24 3141265400 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.2858638058 Aug 25 02:26:19 PM UTC 24 Aug 25 02:51:16 PM UTC 24 3151676800 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.2371867406 Aug 25 02:20:01 PM UTC 24 Aug 25 02:51:23 PM UTC 24 235340100 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.3992741678 Aug 25 02:27:08 PM UTC 24 Aug 25 02:51:37 PM UTC 24 350739700 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.568753409 Aug 25 02:48:02 PM UTC 24 Aug 25 02:51:37 PM UTC 24 10012023800 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1897758872 Aug 25 02:49:46 PM UTC 24 Aug 25 02:51:38 PM UTC 24 10832297400 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2440380889 Aug 25 02:50:18 PM UTC 24 Aug 25 02:51:41 PM UTC 24 2222067100 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.467257731 Aug 25 02:30:30 PM UTC 24 Aug 25 02:52:03 PM UTC 24 190190195700 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2716261357 Aug 25 02:48:26 PM UTC 24 Aug 25 02:52:11 PM UTC 24 10358569400 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3622950509 Aug 25 02:48:16 PM UTC 24 Aug 25 02:52:11 PM UTC 24 39135500 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3666469984 Aug 25 02:48:52 PM UTC 24 Aug 25 02:52:13 PM UTC 24 5632653300 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3272010999 Aug 25 02:44:42 PM UTC 24 Aug 25 02:52:14 PM UTC 24 29566322700 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.597350512 Aug 25 02:51:39 PM UTC 24 Aug 25 02:52:17 PM UTC 24 26195000 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.112632001 Aug 25 02:51:25 PM UTC 24 Aug 25 02:52:17 PM UTC 24 71119700 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.4041907583 Aug 25 02:50:37 PM UTC 24 Aug 25 02:52:27 PM UTC 24 5394219000 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.4250511718 Aug 25 02:48:06 PM UTC 24 Aug 25 02:52:29 PM UTC 24 117063300 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1197549196 Aug 25 02:52:12 PM UTC 24 Aug 25 02:52:36 PM UTC 24 15349300 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1982012969 Aug 25 02:52:03 PM UTC 24 Aug 25 02:52:37 PM UTC 24 51215300 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2739823579 Aug 25 02:51:38 PM UTC 24 Aug 25 02:52:37 PM UTC 24 40756800 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1098878782 Aug 25 02:52:14 PM UTC 24 Aug 25 02:52:39 PM UTC 24 35783500 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.820128155 Aug 25 02:52:12 PM UTC 24 Aug 25 02:52:39 PM UTC 24 19394600 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.902036334 Aug 25 02:51:38 PM UTC 24 Aug 25 02:52:44 PM UTC 24 218563700 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.120065902 Aug 25 02:41:15 PM UTC 24 Aug 25 02:52:54 PM UTC 24 24369120000 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.1532953548 Aug 25 02:46:28 PM UTC 24 Aug 25 02:52:55 PM UTC 24 96038200 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.2348360070 Aug 25 02:46:54 PM UTC 24 Aug 25 02:53:09 PM UTC 24 6994758400 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.1621132477 Aug 25 02:51:42 PM UTC 24 Aug 25 02:53:15 PM UTC 24 1268375400 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.1354834593 Aug 25 02:46:39 PM UTC 24 Aug 25 02:53:18 PM UTC 24 10125213400 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3070762504 Aug 25 02:52:13 PM UTC 24 Aug 25 02:53:20 PM UTC 24 10145819100 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.1606634437 Aug 25 02:26:46 PM UTC 24 Aug 25 02:53:21 PM UTC 24 18140294100 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.3851582415 Aug 25 02:34:05 PM UTC 24 Aug 25 02:53:24 PM UTC 24 1411353200 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4042310970 Aug 25 02:50:53 PM UTC 24 Aug 25 02:53:30 PM UTC 24 556536000 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1540993954 Aug 25 02:53:16 PM UTC 24 Aug 25 02:53:41 PM UTC 24 48411400 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.3599945401 Aug 25 02:30:32 PM UTC 24 Aug 25 02:53:53 PM UTC 24 2819084600 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1395744439 Aug 25 02:34:12 PM UTC 24 Aug 25 02:53:55 PM UTC 24 160188037000 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.2157627482 Aug 25 02:53:24 PM UTC 24 Aug 25 02:54:02 PM UTC 24 29294900 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.2240516357 Aug 25 02:50:15 PM UTC 24 Aug 25 02:54:03 PM UTC 24 56253800 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3881803958 Aug 25 02:52:40 PM UTC 24 Aug 25 02:54:07 PM UTC 24 1978387000 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3712953824 Aug 25 02:53:21 PM UTC 24 Aug 25 02:54:08 PM UTC 24 57320500 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1808297831 Aug 25 02:50:26 PM UTC 24 Aug 25 02:54:09 PM UTC 24 130302400 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.3435698508 Aug 25 02:53:42 PM UTC 24 Aug 25 02:54:13 PM UTC 24 13938800 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1067236860 Aug 25 02:53:54 PM UTC 24 Aug 25 02:54:18 PM UTC 24 18590000 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.1161858751 Aug 25 02:43:19 PM UTC 24 Aug 25 02:54:18 PM UTC 24 76787600 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.2488607958 Aug 25 02:53:56 PM UTC 24 Aug 25 02:54:20 PM UTC 24 15595900 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.1474515118 Aug 25 02:53:23 PM UTC 24 Aug 25 02:54:20 PM UTC 24 114632800 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1799189282 Aug 25 02:43:24 PM UTC 24 Aug 25 02:54:22 PM UTC 24 8222372600 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.2574847916 Aug 25 02:54:04 PM UTC 24 Aug 25 02:54:28 PM UTC 24 20012900 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.574545050 Aug 25 02:50:41 PM UTC 24 Aug 25 02:54:30 PM UTC 24 1978083700 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2476872288 Aug 25 02:53:31 PM UTC 24 Aug 25 02:54:57 PM UTC 24 685158300 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3865363132 Aug 25 02:51:13 PM UTC 24 Aug 25 02:54:57 PM UTC 24 24323768100 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2959147058 Aug 25 02:51:16 PM UTC 24 Aug 25 02:55:19 PM UTC 24 25093095100 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.3536246594 Aug 25 02:54:58 PM UTC 24 Aug 25 02:55:26 PM UTC 24 85532500 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.705546507 Aug 25 02:13:08 PM UTC 24 Aug 25 02:55:30 PM UTC 24 97498847600 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1417122470 Aug 25 02:43:53 PM UTC 24 Aug 25 02:55:33 PM UTC 24 45206416200 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1063622502 Aug 25 02:52:45 PM UTC 24 Aug 25 02:55:35 PM UTC 24 6918141700 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.2268142809 Aug 25 02:51:12 PM UTC 24 Aug 25 02:55:35 PM UTC 24 1889473000 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.3076652828 Aug 25 02:46:52 PM UTC 24 Aug 25 02:55:52 PM UTC 24 14271034300 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.2365280780 Aug 25 02:55:35 PM UTC 24 Aug 25 02:56:02 PM UTC 24 16588300 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.2755853567 Aug 25 02:52:30 PM UTC 24 Aug 25 02:56:03 PM UTC 24 8235791700 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3421669479 Aug 25 02:52:38 PM UTC 24 Aug 25 02:56:05 PM UTC 24 10331728000 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.4066281730 Aug 25 02:54:21 PM UTC 24 Aug 25 02:56:06 PM UTC 24 981460000 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.4186812148 Aug 25 02:55:19 PM UTC 24 Aug 25 02:56:10 PM UTC 24 69330700 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.1871170984 Aug 25 02:54:13 PM UTC 24 Aug 25 02:56:13 PM UTC 24 2478788100 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.784614843 Aug 25 02:55:27 PM UTC 24 Aug 25 02:56:16 PM UTC 24 66299700 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.1486949818 Aug 25 02:55:33 PM UTC 24 Aug 25 02:56:17 PM UTC 24 33477900 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.431063578 Aug 25 02:52:37 PM UTC 24 Aug 25 02:56:17 PM UTC 24 39941000 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.3451713567 Aug 25 02:55:54 PM UTC 24 Aug 25 02:56:18 PM UTC 24 47739100 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.774441817 Aug 25 02:56:03 PM UTC 24 Aug 25 02:56:30 PM UTC 24 48083300 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.2549705796 Aug 25 02:56:07 PM UTC 24 Aug 25 02:56:33 PM UTC 24 38706100 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.2107955959 Aug 25 02:54:08 PM UTC 24 Aug 25 02:56:33 PM UTC 24 45490400 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3316504571 Aug 25 02:54:03 PM UTC 24 Aug 25 02:56:34 PM UTC 24 10020345900 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3254982915 Aug 25 02:55:30 PM UTC 24 Aug 25 02:56:36 PM UTC 24 272625800 ps
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