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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A	0	0	375370398	15627389	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A	0	0	375370398	15627389	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A	0	0	375286767	15627234	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	375370398	343328251	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	375370398	15627389	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	375370398	15627389	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A	0	0	375370398	31254787	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M	0	0	375286767	15627234	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A	0	0	375370398	15627389	0	0
tb.dut.u_flash_hw_if.DisableChk_A	0	0	362792329	3369097	0	43
tb.dut.u_flash_hw_if.ProgRdVerify_A	0	0	358502807	2043529	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq	0	0	375370437	8641	0	0
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq	0	0	375276785	8309	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq	0	0	375370437	8606	0	0
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq	0	0	359424105	8306	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A	0	0	1052	1052	0	0
tb.dut.u_flash_hw_if.u_rma_state_regs_A	0	0	375370437	374583077	0	0
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A	0	0	1052	1052	0	0
tb.dut.u_flash_hw_if.u_state_regs_A	0	0	375370437	374583077	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	369547541	368760181	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	369547541	368729116	0	2751
tb.dut.u_flash_mp.BankEraseData_A	0	0	375370437	8062364	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	375370437	11600662	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	375370437	233441353	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	375370437	261788047	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	375370437	28346694	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	372060438	122236	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	375370437	19663026	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	375370437	156354021	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	375370437	261665783	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	375370437	261665783	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	1052	1052	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	1052	1052	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	1052	1052	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	1052	1052	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	1052	1052	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	1052	1052	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	369525969	368738609	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	369525969	368707694	0	2601
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	369547541	368760181	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	369547541	368729116	0	2751
tb.dut.u_prog_fifo.DataKnown_A	0	0	375370398	163766602	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	163766602	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	369547502	368760142	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	369547502	368760142	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	1052	1052	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	375370398	374583038	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1052	1052	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1052	1052	0	0
tb.dut.u_reg_core.en2addrHit	0	0	378349590	27057876	0	0
tb.dut.u_reg_core.reAfterRv	0	0	378349590	27057859	0	0
tb.dut.u_reg_core.rePulse	0	0	378349590	24661875	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	378349590	377477481	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	378349590	377477481	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	378349551	33427901	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	378349551	43584256	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	378349551	2209400	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	378349551	3565924	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	378349551	3744026	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	378349551	4772528	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	378349551	27413693	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	378349551	35245804	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	378349551	377477442	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1267	1267	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1267	1267	0	0
tb.dut.u_reg_core.wePulse	0	0	378349590	2395984	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	375370437	374583077	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	369547541	368760181	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	369547541	368729116	0	2751
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	369547541	368760181	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	369547541	368729116	0	2751
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	369547541	368760181	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	369547541	368729116	0	2751
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	369547541	368760181	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	369547541	368729116	0	2751
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	375370398	35818303	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	35818303	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnownIfFifoKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.TlOutValidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DataKnown_A	0	0	375370398	31985888	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	31985888	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	375370398	4063617	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	375370398	4063617	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	375370398	33103167	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	33103167	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	375370398	5177102	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	5177102	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.SramReadbackAndIntg	0	0	1052	1052	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	375370398	31985888	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	31985888	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1052	1052	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	369547502	368760142	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	369547502	368760142	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1052	1052	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	375370398	374583038	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1052	1052	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.TlOutValidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	375370398	3539018	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	3539018	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1052	1052	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.TlOutValidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	375370398	3034934	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	374690939	3028318	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	375370398	4767634	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	4767634	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	375203768	4759704	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	4772243	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1052	1052	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	375370398	3034934	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	375370398	374583038	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375370398	3034934	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	375370398	0	0	1047
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	375370398	0	0	1047
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	369547502	368729092	0	2751
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375370398	0	0	1047
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375370398	0	0	1047
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375370398	0	0	1047
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375370398	0	0	1047
tb.dut.u_flash_hw_if.DisableChk_A	0	0	362792329	3369097	0	43

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