Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 24686453 1 T1 305 T2 15 T3 739
full_word 7326998 1 T1 59 T2 2 T3 2340


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 32013151 1 T1 364 T2 17 T3 3079
auto[TlIntgErrCmd] 98 1 T254 2 T255 1 T256 3
auto[TlIntgErrData] 110 1 T254 4 T255 7 T256 3
auto[TlIntgErrBoth] 92 1 T254 4 T255 2 T256 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27693276 1 T1 323 T2 13 T3 1117
auto[1] 4320175 1 T1 41 T2 4 T3 1962


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrCmd]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 23982028 1 T1 302 T2 13 T3 594
auto[TlIntgErrNone] partial auto[1] 704148 1 T1 3 T2 2 T3 145
auto[TlIntgErrNone] full_word auto[0] 3711114 1 T1 21 T3 523 T12 1554
auto[TlIntgErrNone] full_word auto[1] 3615861 1 T1 38 T2 2 T3 1817
auto[TlIntgErrCmd] partial auto[0] 42 1 T256 3 T363 1 T358 2
auto[TlIntgErrCmd] partial auto[1] 53 1 T254 2 T255 1 T363 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T363 1 T364 1 T359 1
auto[TlIntgErrData] partial auto[0] 51 1 T254 2 T255 3 T256 2
auto[TlIntgErrData] partial auto[1] 48 1 T254 1 T255 2 T256 1
auto[TlIntgErrData] full_word auto[0] 5 1 T255 1 T356 3 T362 1
auto[TlIntgErrData] full_word auto[1] 6 1 T254 1 T255 1 T358 1
auto[TlIntgErrBoth] partial auto[0] 31 1 T254 2 T256 1 T363 1
auto[TlIntgErrBoth] partial auto[1] 52 1 T254 2 T255 2 T256 3
auto[TlIntgErrBoth] full_word auto[0] 5 1 T352 1 T365 1 T354 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T358 1 T365 1 T359 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 16293 1 T108 557 T71 42 T111 446
full_word 3751056 1 T2 10 T3 275 T13 86


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3767065 1 T2 10 T3 275 T13 86
auto[TlIntgErrCmd] 93 1 T254 4 T255 3 T256 5
auto[TlIntgErrData] 96 1 T254 2 T255 3 T256 2
auto[TlIntgErrBoth] 95 1 T254 4 T255 4 T256 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3746480 1 T2 10 T3 275 T13 86
auto[1] 20869 1 T108 699 T71 56 T111 553


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 989 1 T108 72 T71 3 T111 35
auto[TlIntgErrNone] partial auto[1] 15045 1 T108 485 T71 39 T111 411
auto[TlIntgErrNone] full_word auto[0] 3745369 1 T2 10 T3 275 T13 86
auto[TlIntgErrNone] full_word auto[1] 5662 1 T108 214 T71 17 T111 142
auto[TlIntgErrCmd] partial auto[0] 30 1 T255 2 T256 1 T363 2
auto[TlIntgErrCmd] partial auto[1] 55 1 T254 4 T255 1 T256 3
auto[TlIntgErrCmd] full_word auto[0] 4 1 T352 1 T354 1 T360 1
auto[TlIntgErrCmd] full_word auto[1] 4 1 T256 1 T359 1 T366 1
auto[TlIntgErrData] partial auto[0] 48 1 T254 1 T255 2 T256 1
auto[TlIntgErrData] partial auto[1] 33 1 T254 1 T256 1 T363 1
auto[TlIntgErrData] full_word auto[0] 8 1 T255 1 T353 2 T356 1
auto[TlIntgErrData] full_word auto[1] 7 1 T364 1 T354 2 T367 2
auto[TlIntgErrBoth] partial auto[0] 31 1 T254 3 T255 2 T256 2
auto[TlIntgErrBoth] partial auto[1] 62 1 T254 1 T255 2 T256 1
auto[TlIntgErrBoth] full_word auto[0] 1 1 T356 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 1 1 T368 1 - - - -

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