Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600

47 always_comb begin 48 1/1 incr_buf_sel = '0; Tests: T1 T2 T3  49 1/1 decr_buf_sel = '0; Tests: T1 T2 T3  50 1/1 for (int unsigned i = 0; i < NumBuf; i++) begin Tests: T1 T2 T3  51 1/1 if (wr_buf_i[i]) begin Tests: T1 T2 T3  52 1/1 incr_buf_sel = buf_mux_cnt[i]; Tests: T1 T2 T3  53 end MISSING_ELSE 54 1/1 if (rd_buf_i[i]) begin Tests: T1 T2 T3  55 1/1 decr_buf_sel = buf_mux_cnt[i]; Tests: T1 T2 T3  56 end MISSING_ELSE 57 end 58 end // always_comb 59 60 logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt; 61 1/1 assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel]; Tests: T1 T2 T3  62 1/1 assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel]; Tests: T1 T2 T3  63 64 logic cnt_incr, cnt_decr; 65 1/1 assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth); Tests: T1 T2 T3  66 1/1 assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0); Tests: T1 T2 T3  67 68 //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0); 69 70 logic fin_cnt_incr, fin_cnt_decr; 71 1/1 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr; Tests: T1 T2 T3  72 1/1 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr; Tests: T1 T2 T3  73 74 // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo 75 always_ff @(posedge clk_i or negedge rst_ni) begin 76 1/1 if (!rst_ni) begin Tests: T1 T2 T3  77 1/1 buf_dependency_cnt <= '0; Tests: T1 T2 T3  78 end else begin 79 1/1 if (fin_cnt_incr) begin Tests: T1 T2 T3  80 1/1 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1; Tests: T1 T2 T3  81 end MISSING_ELSE 82 1/1 if (fin_cnt_decr) begin Tests: T1 T2 T3  83 1/1 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1; Tests: T1 T2 T3  84 end MISSING_ELSE 85 end 86 end 87 88 // per buffer dependency determination 89 always_comb begin 90 1/1 dependency_o = '0; Tests: T1 T2 T3  91 1/1 for (int i = 0; i < NumBuf; i++) begin Tests: T1 T2 T3  92 1/1 dependency_o[i] = |buf_dependency_cnt[i]; Tests: T1 T2 T3  93 end 94 end 95 96 // all buffer entries currently have a dependency 97 1/1 assign all_dependency_o = &dependency_o; Tests: T1 T2 T3  98 99 100 // If there are more buffers than there are number of response fifo entries, we an never have 101 // a fully dependent condition 102 `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o) 103 104 // We should never attempt to increment when at max value 105 `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth) 106 107 // We should never attempt to decrement when at min value 108 `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0)) 109 110 // The total number of dependent buffers cannot never exceed the size of response queue 111 `ifdef INC_ASSERT 112 //VCS coverage off 113 // pragma coverage off 114 logic [31:0] assert_cnt; 115 always_comb begin 116 unreachable assert_cnt = '0; 117 unreachable for (int unsigned i = 0; i < NumBuf; i++) begin 118 unreachable assert_cnt = assert_cnt + dependency_o[i];

Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T13
11CoveredT1,T2,T3

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT2,T3,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00


71 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


72 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


51 if (wr_buf_i[i]) begin -1- 52 incr_buf_sel = buf_mux_cnt[i]; ==> 53 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


54 if (rd_buf_i[i]) begin -1- 55 decr_buf_sel = buf_mux_cnt[i]; ==> 56 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


76 if (!rst_ni) begin -1- 77 buf_dependency_cnt <= '0; ==> 78 end else begin 79 if (fin_cnt_incr) begin -2- 80 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1; ==> 81 end MISSING_ELSE ==> 82 if (fin_cnt_decr) begin -3- 83 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1; ==> 84 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 750740796 6572350 0 0
BufferDepRsp_A 750740796 749166076 0 0
BufferIncrOverFlow_A 750740796 6572366 0 0
DepBufferRspOrder_A 750740798 16660330 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 750740796 6572350 0 0
T1 1858 20 0 0
T2 1367 10 0 0
T3 52112 694 0 0
T12 185548 1384 0 0
T13 6124 129 0 0
T14 0 765 0 0
T16 322998 2352 0 0
T17 7162 0 0 0
T18 4780 7 0 0
T19 4596 146 0 0
T20 164470 41 0 0
T23 5492 188 0 0
T50 0 9522 0 0
T58 1993 146 0 0
T62 0 146 0 0
T63 0 977 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 750740796 749166076 0 0
T1 3716 3578 0 0
T2 2734 2592 0 0
T3 52112 52004 0 0
T12 185548 176366 0 0
T13 6124 5988 0 0
T16 322998 322878 0 0
T17 7162 7040 0 0
T18 4780 4584 0 0
T19 4596 4436 0 0
T20 164470 164210 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 750740796 6572366 0 0
T1 1858 20 0 0
T2 1367 10 0 0
T3 52112 694 0 0
T12 185548 1384 0 0
T13 6124 129 0 0
T14 0 765 0 0
T16 322998 2352 0 0
T17 7162 0 0 0
T18 4780 7 0 0
T19 4596 146 0 0
T20 164470 42 0 0
T23 5492 188 0 0
T50 0 9522 0 0
T58 1993 146 0 0
T62 0 146 0 0
T63 0 977 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 750740798 16660330 0 0
T1 1858 52 0 0
T2 1367 42 0 0
T3 52112 726 0 0
T12 185548 3272 0 0
T13 6124 161 0 0
T14 0 556 0 0
T16 322998 2384 0 0
T17 7162 32 0 0
T18 4780 39 0 0
T19 4596 178 0 0
T20 164470 73 0 0
T23 5492 188 0 0
T50 0 9522 0 0
T58 1993 0 0 0
T62 0 146 0 0
T63 0 977 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600

47 always_comb begin 48 1/1 incr_buf_sel = '0; Tests: T1 T2 T3  49 1/1 decr_buf_sel = '0; Tests: T1 T2 T3  50 1/1 for (int unsigned i = 0; i < NumBuf; i++) begin Tests: T1 T2 T3  51 1/1 if (wr_buf_i[i]) begin Tests: T1 T2 T3  52 1/1 incr_buf_sel = buf_mux_cnt[i]; Tests: T1 T2 T3  53 end MISSING_ELSE 54 1/1 if (rd_buf_i[i]) begin Tests: T1 T2 T3  55 1/1 decr_buf_sel = buf_mux_cnt[i]; Tests: T1 T2 T3  56 end MISSING_ELSE 57 end 58 end // always_comb 59 60 logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt; 61 1/1 assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel]; Tests: T1 T2 T3  62 1/1 assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel]; Tests: T1 T2 T3  63 64 logic cnt_incr, cnt_decr; 65 1/1 assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth); Tests: T1 T2 T3  66 1/1 assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0); Tests: T1 T2 T3  67 68 //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0); 69 70 logic fin_cnt_incr, fin_cnt_decr; 71 1/1 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr; Tests: T1 T2 T3  72 1/1 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr; Tests: T1 T2 T3  73 74 // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo 75 always_ff @(posedge clk_i or negedge rst_ni) begin 76 1/1 if (!rst_ni) begin Tests: T1 T2 T3  77 1/1 buf_dependency_cnt <= '0; Tests: T1 T2 T3  78 end else begin 79 1/1 if (fin_cnt_incr) begin Tests: T1 T2 T3  80 1/1 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1; Tests: T1 T2 T3  81 end MISSING_ELSE 82 1/1 if (fin_cnt_decr) begin Tests: T1 T2 T3  83 1/1 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1; Tests: T1 T2 T3  84 end MISSING_ELSE 85 end 86 end 87 88 // per buffer dependency determination 89 always_comb begin 90 1/1 dependency_o = '0; Tests: T1 T2 T3  91 1/1 for (int i = 0; i < NumBuf; i++) begin Tests: T1 T2 T3  92 1/1 dependency_o[i] = |buf_dependency_cnt[i]; Tests: T1 T2 T3  93 end 94 end 95 96 // all buffer entries currently have a dependency 97 1/1 assign all_dependency_o = &dependency_o; Tests: T1 T2 T3  98 99 100 // If there are more buffers than there are number of response fifo entries, we an never have 101 // a fully dependent condition 102 `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o) 103 104 // We should never attempt to increment when at max value 105 `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth) 106 107 // We should never attempt to decrement when at min value 108 `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0)) 109 110 // The total number of dependent buffers cannot never exceed the size of response queue 111 `ifdef INC_ASSERT 112 //VCS coverage off 113 // pragma coverage off 114 logic [31:0] assert_cnt; 115 always_comb begin 116 unreachable assert_cnt = '0; 117 unreachable for (int unsigned i = 0; i < NumBuf; i++) begin 118 unreachable assert_cnt = assert_cnt + dependency_o[i];

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T13
11CoveredT1,T2,T3

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT2,T3,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00


71 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


72 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


51 if (wr_buf_i[i]) begin -1- 52 incr_buf_sel = buf_mux_cnt[i]; ==> 53 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


54 if (rd_buf_i[i]) begin -1- 55 decr_buf_sel = buf_mux_cnt[i]; ==> 56 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


76 if (!rst_ni) begin -1- 77 buf_dependency_cnt <= '0; ==> 78 end else begin 79 if (fin_cnt_incr) begin -2- 80 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1; ==> 81 end MISSING_ELSE ==> 82 if (fin_cnt_decr) begin -3- 83 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1; ==> 84 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 375370398 3592973 0 0
BufferDepRsp_A 375370398 374583038 0 0
BufferIncrOverFlow_A 375370398 3592983 0 0
DepBufferRspOrder_A 375370398 9111448 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370398 3592973 0 0
T1 1858 20 0 0
T2 1367 10 0 0
T3 26056 194 0 0
T12 92774 1384 0 0
T13 3062 63 0 0
T14 0 209 0 0
T16 161499 1120 0 0
T17 3581 0 0 0
T18 2390 7 0 0
T19 2298 0 0 0
T20 82235 20 0 0
T58 0 146 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370398 374583038 0 0
T1 1858 1789 0 0
T2 1367 1296 0 0
T3 26056 26002 0 0
T12 92774 88183 0 0
T13 3062 2994 0 0
T16 161499 161439 0 0
T17 3581 3520 0 0
T18 2390 2292 0 0
T19 2298 2218 0 0
T20 82235 82105 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370398 3592983 0 0
T1 1858 20 0 0
T2 1367 10 0 0
T3 26056 194 0 0
T12 92774 1384 0 0
T13 3062 63 0 0
T14 0 209 0 0
T16 161499 1120 0 0
T17 3581 0 0 0
T18 2390 7 0 0
T19 2298 0 0 0
T20 82235 21 0 0
T58 0 146 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370398 9111448 0 0
T1 1858 52 0 0
T2 1367 42 0 0
T3 26056 226 0 0
T12 92774 3272 0 0
T13 3062 95 0 0
T16 161499 1152 0 0
T17 3581 32 0 0
T18 2390 39 0 0
T19 2298 32 0 0
T20 82235 52 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600

47 always_comb begin 48 1/1 incr_buf_sel = '0; Tests: T1 T2 T3  49 1/1 decr_buf_sel = '0; Tests: T1 T2 T3  50 1/1 for (int unsigned i = 0; i < NumBuf; i++) begin Tests: T1 T2 T3  51 1/1 if (wr_buf_i[i]) begin Tests: T1 T2 T3  52 1/1 incr_buf_sel = buf_mux_cnt[i]; Tests: T3 T13 T16  53 end MISSING_ELSE 54 1/1 if (rd_buf_i[i]) begin Tests: T1 T2 T3  55 1/1 decr_buf_sel = buf_mux_cnt[i]; Tests: T3 T13 T16  56 end MISSING_ELSE 57 end 58 end // always_comb 59 60 logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt; 61 1/1 assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel]; Tests: T1 T2 T3  62 1/1 assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel]; Tests: T1 T2 T3  63 64 logic cnt_incr, cnt_decr; 65 1/1 assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth); Tests: T1 T2 T3  66 1/1 assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0); Tests: T1 T2 T3  67 68 //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0); 69 70 logic fin_cnt_incr, fin_cnt_decr; 71 1/1 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr; Tests: T1 T2 T3  72 1/1 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr; Tests: T1 T2 T3  73 74 // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo 75 always_ff @(posedge clk_i or negedge rst_ni) begin 76 1/1 if (!rst_ni) begin Tests: T1 T2 T3  77 1/1 buf_dependency_cnt <= '0; Tests: T1 T2 T3  78 end else begin 79 1/1 if (fin_cnt_incr) begin Tests: T1 T2 T3  80 1/1 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1; Tests: T3 T13 T16  81 end MISSING_ELSE 82 1/1 if (fin_cnt_decr) begin Tests: T1 T2 T3  83 1/1 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1; Tests: T3 T13 T16  84 end MISSING_ELSE 85 end 86 end 87 88 // per buffer dependency determination 89 always_comb begin 90 1/1 dependency_o = '0; Tests: T1 T2 T3  91 1/1 for (int i = 0; i < NumBuf; i++) begin Tests: T1 T2 T3  92 1/1 dependency_o[i] = |buf_dependency_cnt[i]; Tests: T1 T2 T3  93 end 94 end 95 96 // all buffer entries currently have a dependency 97 1/1 assign all_dependency_o = &dependency_o; Tests: T1 T2 T3  98 99 100 // If there are more buffers than there are number of response fifo entries, we an never have 101 // a fully dependent condition 102 `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o) 103 104 // We should never attempt to increment when at max value 105 `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth) 106 107 // We should never attempt to decrement when at min value 108 `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0)) 109 110 // The total number of dependent buffers cannot never exceed the size of response queue 111 `ifdef INC_ASSERT 112 //VCS coverage off 113 // pragma coverage off 114 logic [31:0] assert_cnt; 115 always_comb begin 116 unreachable assert_cnt = '0; 117 unreachable for (int unsigned i = 0; i < NumBuf; i++) begin 118 unreachable assert_cnt = assert_cnt + dependency_o[i];

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT118,T116,T82
101CoveredT1,T2,T3
110Not Covered
111CoveredT3,T13,T16

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T13,T16
110Not Covered
111CoveredT3,T13,T16

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T13,T16
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T23,T14
11CoveredT3,T13,T16

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T13,T16
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT3,T23,T14
10CoveredT1,T2,T3
11CoveredT3,T13,T16

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00


71 assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T13,T16


72 assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T13,T16


51 if (wr_buf_i[i]) begin -1- 52 incr_buf_sel = buf_mux_cnt[i]; ==> 53 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T3,T13,T16
0 Covered T1,T2,T3


54 if (rd_buf_i[i]) begin -1- 55 decr_buf_sel = buf_mux_cnt[i]; ==> 56 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T3,T13,T16
0 Covered T1,T2,T3


76 if (!rst_ni) begin -1- 77 buf_dependency_cnt <= '0; ==> 78 end else begin 79 if (fin_cnt_incr) begin -2- 80 buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1; ==> 81 end MISSING_ELSE ==> 82 if (fin_cnt_decr) begin -3- 83 buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1; ==> 84 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T13,T16
0 0 - Covered T1,T2,T3
0 - 1 Covered T3,T13,T16
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 375370398 2979377 0 0
BufferDepRsp_A 375370398 374583038 0 0
BufferIncrOverFlow_A 375370398 2979383 0 0
DepBufferRspOrder_A 375370400 7548882 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370398 2979377 0 0
T3 26056 500 0 0
T12 92774 0 0 0
T13 3062 66 0 0
T14 0 556 0 0
T16 161499 1232 0 0
T17 3581 0 0 0
T18 2390 0 0 0
T19 2298 146 0 0
T20 82235 21 0 0
T23 5492 188 0 0
T50 0 9522 0 0
T58 1993 0 0 0
T62 0 146 0 0
T63 0 977 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370398 374583038 0 0
T1 1858 1789 0 0
T2 1367 1296 0 0
T3 26056 26002 0 0
T12 92774 88183 0 0
T13 3062 2994 0 0
T16 161499 161439 0 0
T17 3581 3520 0 0
T18 2390 2292 0 0
T19 2298 2218 0 0
T20 82235 82105 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370398 2979383 0 0
T3 26056 500 0 0
T12 92774 0 0 0
T13 3062 66 0 0
T14 0 556 0 0
T16 161499 1232 0 0
T17 3581 0 0 0
T18 2390 0 0 0
T19 2298 146 0 0
T20 82235 21 0 0
T23 5492 188 0 0
T50 0 9522 0 0
T58 1993 0 0 0
T62 0 146 0 0
T63 0 977 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375370400 7548882 0 0
T3 26056 500 0 0
T12 92774 0 0 0
T13 3062 66 0 0
T14 0 556 0 0
T16 161499 1232 0 0
T17 3581 0 0 0
T18 2390 0 0 0
T19 2298 146 0 0
T20 82235 21 0 0
T23 5492 188 0 0
T50 0 9522 0 0
T58 1993 0 0 0
T62 0 146 0 0
T63 0 977 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%