Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T50
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T13

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T13

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1501481592	1498332152	0	0
CheckNGreaterZero_A	4208	4208	0	0
GntImpliesReady_A	1501481592	402049768	0	0
GntImpliesValid_A	1501481592	402049768	0	0
GrantKnown_A	1501481592	1498332152	0	0
IdxKnown_A	1501481592	1498332152	0	0
IndexIsCorrect_A	1501481592	402049768	0	0
NoReadyValidNoGrant_A	1501481592	167632731	0	0
Priority_A	1501481592	425989523	0	0
ReadyAndValidImplyGrant_A	1501481592	402049768	0	0
ReqAndReadyImplyGrant_A	1501481592	402049768	0	0
ReqImpliesValid_A	1501481592	425989523	0	0
ValidKnown_A	1501481592	1498332152	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	1498332152	0	0
T1	7432	7156	0	0
T2	5468	5184	0	0
T3	104224	104008	0	0
T12	371096	352732	0	0
T13	12248	11976	0	0
T16	645996	645756	0	0
T17	14324	14080	0	0
T18	9560	9168	0	0
T19	9192	8872	0	0
T20	328940	328420	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4208	4208	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	402049768	0	0
T1	3716	1178	0	0
T2	2734	84	0	0
T3	104224	1452	0	0
T12	371096	76140	0	0
T13	12248	2960	0	0
T14	0	49628	0	0
T16	645996	109164	0	0
T17	14324	4434	0	0
T18	9560	2170	0	0
T19	9192	356	0	0
T20	328940	42012	0	0
T23	10984	5416	0	0
T58	3986	0	0	0
T62	0	292	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	402049768	0	0
T1	3716	1178	0	0
T2	2734	84	0	0
T3	104224	1452	0	0
T12	371096	76140	0	0
T13	12248	2960	0	0
T14	0	49628	0	0
T16	645996	109164	0	0
T17	14324	4434	0	0
T18	9560	2170	0	0
T19	9192	356	0	0
T20	328940	42012	0	0
T23	10984	5416	0	0
T58	3986	0	0	0
T62	0	292	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	1498332152	0	0
T1	7432	7156	0	0
T2	5468	5184	0	0
T3	104224	104008	0	0
T12	371096	352732	0	0
T13	12248	11976	0	0
T16	645996	645756	0	0
T17	14324	14080	0	0
T18	9560	9168	0	0
T19	9192	8872	0	0
T20	328940	328420	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	1498332152	0	0
T1	7432	7156	0	0
T2	5468	5184	0	0
T3	104224	104008	0	0
T12	371096	352732	0	0
T13	12248	11976	0	0
T16	645996	645756	0	0
T17	14324	14080	0	0
T18	9560	9168	0	0
T19	9192	8872	0	0
T20	328940	328420	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	402049768	0	0
T1	3716	1178	0	0
T2	2734	84	0	0
T3	104224	1452	0	0
T12	371096	76140	0	0
T13	12248	2960	0	0
T14	0	49628	0	0
T16	645996	109164	0	0
T17	14324	4434	0	0
T18	9560	2170	0	0
T19	9192	356	0	0
T20	328940	42012	0	0
T23	10984	5416	0	0
T58	3986	0	0	0
T62	0	292	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	167632731	0	0
T1	3716	316	0	0
T2	2734	286	0	0
T3	104224	2352	0	0
T12	371096	21808	0	0
T13	12248	488	0	0
T14	0	2688	0	0
T16	645996	7312	0	0
T17	14324	256	0	0
T18	9560	278	0	0
T19	9192	656	0	0
T20	328940	420	0	0
T23	10984	584	0	0
T50	0	24126	0	0
T58	3986	0	0	0
T62	0	736	0	0
T63	0	4900	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	425989523	0	0
T1	3716	1178	0	0
T2	2734	84	0	0
T3	104224	1452	0	0
T12	371096	76140	0	0
T13	12248	2970	0	0
T14	0	49664	0	0
T16	645996	109164	0	0
T17	14324	4434	0	0
T18	9560	2170	0	0
T19	9192	356	0	0
T20	328940	42012	0	0
T23	10984	5416	0	0
T58	3986	0	0	0
T62	0	292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	402049768	0	0
T1	3716	1178	0	0
T2	2734	84	0	0
T3	104224	1452	0	0
T12	371096	76140	0	0
T13	12248	2960	0	0
T14	0	49628	0	0
T16	645996	109164	0	0
T17	14324	4434	0	0
T18	9560	2170	0	0
T19	9192	356	0	0
T20	328940	42012	0	0
T23	10984	5416	0	0
T58	3986	0	0	0
T62	0	292	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	402049768	0	0
T1	3716	1178	0	0
T2	2734	84	0	0
T3	104224	1452	0	0
T12	371096	76140	0	0
T13	12248	2960	0	0
T14	0	49628	0	0
T16	645996	109164	0	0
T17	14324	4434	0	0
T18	9560	2170	0	0
T19	9192	356	0	0
T20	328940	42012	0	0
T23	10984	5416	0	0
T58	3986	0	0	0
T62	0	292	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	425989523	0	0
T1	3716	1178	0	0
T2	2734	84	0	0
T3	104224	1452	0	0
T12	371096	76140	0	0
T13	12248	2970	0	0
T14	0	49664	0	0
T16	645996	109164	0	0
T17	14324	4434	0	0
T18	9560	2170	0	0
T19	9192	356	0	0
T20	328940	42012	0	0
T23	10984	5416	0	0
T58	3986	0	0	0
T62	0	292	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1501481592	1498332152	0	0
T1	7432	7156	0	0
T2	5468	5184	0	0
T3	104224	104008	0	0
T12	371096	352732	0	0
T13	12248	11976	0	0
T16	645996	645756	0	0
T17	14324	14080	0	0
T18	9560	9168	0	0
T19	9192	8872	0	0
T20	328940	328420	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T50
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T13

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T13

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375370398	374583038	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375370398	105375852	0	0
GntImpliesValid_A	375370398	105375852	0	0
GrantKnown_A	375370398	374583038	0	0
IdxKnown_A	375370398	374583038	0	0
IndexIsCorrect_A	375370398	105375852	0	0
NoReadyValidNoGrant_A	375370398	43866953	0	0
Priority_A	375370398	111361243	0	0
ReadyAndValidImplyGrant_A	375370398	105375852	0	0
ReqAndReadyImplyGrant_A	375370398	105375852	0	0
ReqImpliesValid_A	375370398	111361243	0	0
ValidKnown_A	375370398	374583038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375852	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375852	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375852	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	43866953	0	0
T1	1858	158	0	0
T2	1367	143	0	0
T3	26056	424	0	0
T12	92774	10904	0	0
T13	3062	183	0	0
T16	161499	1808	0	0
T17	3581	128	0	0
T18	2390	139	0	0
T19	2298	128	0	0
T20	82235	168	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	111361243	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	701	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375852	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375852	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	111361243	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	701	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T50
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T13

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T13

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375370398	374583038	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375370398	105375862	0	0
GntImpliesValid_A	375370398	105375862	0	0
GrantKnown_A	375370398	374583038	0	0
IdxKnown_A	375370398	374583038	0	0
IndexIsCorrect_A	375370398	105375862	0	0
NoReadyValidNoGrant_A	375370398	43866946	0	0
Priority_A	375370398	111361260	0	0
ReadyAndValidImplyGrant_A	375370398	105375862	0	0
ReqAndReadyImplyGrant_A	375370398	105375862	0	0
ReqImpliesValid_A	375370398	111361260	0	0
ValidKnown_A	375370398	374583038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375862	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375862	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375862	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	43866946	0	0
T1	1858	158	0	0
T2	1367	143	0	0
T3	26056	424	0	0
T12	92774	10904	0	0
T13	3062	183	0	0
T16	161499	1808	0	0
T17	3581	128	0	0
T18	2390	139	0	0
T19	2298	128	0	0
T20	82235	168	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	111361260	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	701	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375862	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	105375862	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	700	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	111361260	0	0
T1	1858	589	0	0
T2	1367	42	0	0
T3	26056	226	0	0
T12	92774	38070	0	0
T13	3062	701	0	0
T16	161499	25932	0	0
T17	3581	32	0	0
T18	2390	208	0	0
T19	2298	32	0	0
T20	82235	9779	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T16
1	0	Covered	T3,T13,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T13,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T13,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T50
1	0	Covered	T3,T13,T16
1	1	Covered	T3,T13,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T13,T23
1	1	Covered	T3,T13,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T50
1	1	Covered	T3,T13,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T13,T23

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T13,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375370398	374583038	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375370398	95649027	0	0
GntImpliesValid_A	375370398	95649027	0	0
GrantKnown_A	375370398	374583038	0	0
IdxKnown_A	375370398	374583038	0	0
IndexIsCorrect_A	375370398	95649027	0	0
NoReadyValidNoGrant_A	375370398	39949416	0	0
Priority_A	375370398	101633510	0	0
ReadyAndValidImplyGrant_A	375370398	95649027	0	0
ReqAndReadyImplyGrant_A	375370398	95649027	0	0
ReqImpliesValid_A	375370398	101633510	0	0
ValidKnown_A	375370398	374583038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	39949416	0	0
T3	26056	752	0	0
T12	92774	0	0	0
T13	3062	61	0	0
T14	0	1344	0	0
T16	161499	1848	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	200	0	0
T20	82235	42	0	0
T23	5492	292	0	0
T50	0	12063	0	0
T58	1993	0	0	0
T62	0	368	0	0
T63	0	2450	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	101633510	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	784	0	0
T14	0	24832	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	101633510	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	784	0	0
T14	0	24832	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T16
1	0	Covered	T3,T13,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T13,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T13,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T50
1	0	Covered	T3,T13,T16
1	1	Covered	T3,T13,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T13,T23
1	1	Covered	T3,T13,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T50
1	1	Covered	T3,T13,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T13,T23

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T13,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375370398	374583038	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	375370398	95649027	0	0
GntImpliesValid_A	375370398	95649027	0	0
GrantKnown_A	375370398	374583038	0	0
IdxKnown_A	375370398	374583038	0	0
IndexIsCorrect_A	375370398	95649027	0	0
NoReadyValidNoGrant_A	375370398	39949416	0	0
Priority_A	375370398	101633510	0	0
ReadyAndValidImplyGrant_A	375370398	95649027	0	0
ReqAndReadyImplyGrant_A	375370398	95649027	0	0
ReqImpliesValid_A	375370398	101633510	0	0
ValidKnown_A	375370398	374583038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	39949416	0	0
T3	26056	752	0	0
T12	92774	0	0	0
T13	3062	61	0	0
T14	0	1344	0	0
T16	161499	1848	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	200	0	0
T20	82235	42	0	0
T23	5492	292	0	0
T50	0	12063	0	0
T58	1993	0	0	0
T62	0	368	0	0
T63	0	2450	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	101633510	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	784	0	0
T14	0	24832	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	95649027	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	780	0	0
T14	0	24814	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	101633510	0	0
T3	26056	500	0	0
T12	92774	0	0	0
T13	3062	784	0	0
T14	0	24832	0	0
T16	161499	28650	0	0
T17	3581	2185	0	0
T18	2390	877	0	0
T19	2298	146	0	0
T20	82235	11227	0	0
T23	5492	2708	0	0
T58	1993	0	0	0
T62	0	146	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	374583038	0	0
T1	1858	1789	0	0
T2	1367	1296	0	0
T3	26056	26002	0	0
T12	92774	88183	0	0
T13	3062	2994	0	0
T16	161499	161439	0	0
T17	3581	3520	0	0
T18	2390	2292	0	0
T19	2298	2218	0	0
T20	82235	82105	0	0