Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T81 T11 
47         1/1                out_o.err <= '0;
           Tests:       T10 T81 T11 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T1 T12 T13 
50         1/1                out_o.err <= '0;
           Tests:       T1 T12 T13 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T2 T3 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T2 T3 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T2 T3 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T2 T3 
56         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T2 T3 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T2 T3 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T2 T3 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T81,T82,T83

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T12,T13

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T81,T11
0	0	1	-	-	Covered	T1,T12,T13
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	5050419	0	0
UpdateCheck_A	2147483647	5050403	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5050419	0	0
T1	7432	10	0	0
T2	5468	5	0	0
T3	208448	378	0	0
T12	742192	656	0	0
T13	24496	70	0	0
T14	0	391	0	0
T16	1291992	1176	0	0
T17	28648	0	0	0
T18	19120	4	0	0
T19	18384	54	0	0
T20	657880	42	0	0
T23	21968	104	0	0
T50	0	9128	0	0
T58	7972	74	0	0
T62	0	74	0	0
T63	0	491	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5050403	0	0
T1	7432	10	0	0
T2	5468	5	0	0
T3	208448	378	0	0
T12	742192	656	0	0
T13	24496	70	0	0
T14	0	391	0	0
T16	1291992	1176	0	0
T17	28648	0	0	0
T18	19120	4	0	0
T19	18384	54	0	0
T20	657880	41	0	0
T23	21968	104	0	0
T50	0	9128	0	0
T58	7972	74	0	0
T62	0	74	0	0
T63	0	491	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T81 T11 
47         1/1                out_o.err <= '0;
           Tests:       T10 T81 T11 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T1 T12 T13 
50         1/1                out_o.err <= '0;
           Tests:       T1 T12 T13 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T2 T3 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T2 T3 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T2 T3 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T2 T3 
56         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T2 T3 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T2 T3 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T2 T3 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T81,T82,T83

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T12,T13

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T81,T11
0	0	1	-	-	Covered	T1,T12,T13
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	670411	0	0
UpdateCheck_A	375370398	670409	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	670411	0	0
T1	1858	3	0	0
T2	1367	2	0	0
T3	26056	27	0	0
T12	92774	164	0	0
T13	3062	8	0	0
T14	0	28	0	0
T16	161499	145	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	6	0	0
T58	0	19	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	670409	0	0
T1	1858	3	0	0
T2	1367	2	0	0
T3	26056	27	0	0
T12	92774	164	0	0
T13	3062	8	0	0
T14	0	28	0	0
T16	161499	145	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	5	0	0
T58	0	19	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T81 T11 
47         1/1                out_o.err <= '0;
           Tests:       T10 T81 T11 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T1 T12 T13 
50         1/1                out_o.err <= '0;
           Tests:       T1 T12 T13 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T2 T3 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T2 T3 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T2 T3 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T2 T3 
56         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T2 T3 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T2 T3 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T2 T3 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T81,T82,T83

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T12,T13

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T81,T11
0	0	1	-	-	Covered	T1,T12,T13
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	670329	0	0
UpdateCheck_A	375370398	670324	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	670329	0	0
T1	1858	3	0	0
T2	1367	1	0	0
T3	26056	26	0	0
T12	92774	164	0	0
T13	3062	8	0	0
T14	0	26	0	0
T16	161499	144	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	5	0	0
T58	0	19	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	670324	0	0
T1	1858	3	0	0
T2	1367	1	0	0
T3	26056	26	0	0
T12	92774	164	0	0
T13	3062	8	0	0
T14	0	26	0	0
T16	161499	144	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	5	0	0
T58	0	19	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T81 T11 
47         1/1                out_o.err <= '0;
           Tests:       T10 T81 T11 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T1 T12 T13 
50         1/1                out_o.err <= '0;
           Tests:       T1 T12 T13 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T2 T3 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T2 T3 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T2 T3 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T2 T3 
56         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T2 T3 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T2 T3 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T2 T3 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T81,T82,T83

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T12,T13

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T81,T11
0	0	1	-	-	Covered	T1,T12,T13
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	670189	0	0
UpdateCheck_A	375370398	670186	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	670189	0	0
T1	1858	2	0	0
T2	1367	1	0	0
T3	26056	26	0	0
T12	92774	164	0	0
T13	3062	8	0	0
T14	0	27	0	0
T16	161499	144	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	5	0	0
T58	0	18	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	670186	0	0
T1	1858	2	0	0
T2	1367	1	0	0
T3	26056	26	0	0
T12	92774	164	0	0
T13	3062	8	0	0
T14	0	27	0	0
T16	161499	144	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	5	0	0
T58	0	18	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T11 T82 
47         1/1                out_o.err <= '0;
           Tests:       T10 T11 T82 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T1 T12 T13 
50         1/1                out_o.err <= '0;
           Tests:       T1 T12 T13 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T2 T3 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T2 T3 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T2 T3 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T2 T3 
56         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T2 T3 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T2 T3 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T2 T3 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T82,T83,T76

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T12,T13

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T11,T82
0	0	1	-	-	Covered	T1,T12,T13
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	669727	0	0
UpdateCheck_A	375370398	669727	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	669727	0	0
T1	1858	2	0	0
T2	1367	1	0	0
T3	26056	26	0	0
T12	92774	164	0	0
T13	3062	7	0	0
T14	0	27	0	0
T16	161499	127	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	5	0	0
T58	0	18	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	669727	0	0
T1	1858	2	0	0
T2	1367	1	0	0
T3	26056	26	0	0
T12	92774	164	0	0
T13	3062	7	0	0
T14	0	27	0	0
T16	161499	127	0	0
T17	3581	0	0	0
T18	2390	1	0	0
T19	2298	0	0	0
T20	82235	5	0	0
T58	0	18	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T11 T82 
47         1/1                out_o.err <= '0;
           Tests:       T10 T11 T82 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T13 T16 T23 
50         1/1                out_o.err <= '0;
           Tests:       T13 T16 T23 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T13 T16 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T13 T16 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T13 T16 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T13 T16 
56         1/1                out_o.err <= '0;
           Tests:       T3 T13 T16 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T13 T16 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T13 T16 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T13 T16 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T82,T83,T76

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T16

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T16,T23

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T11,T82
0	0	1	-	-	Covered	T13,T16,T23
0	0	0	1	-	Covered	T3,T13,T16
0	0	0	0	1	Covered	T3,T13,T16
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	592710	0	0
UpdateCheck_A	375370398	592707	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	592710	0	0
T3	26056	69	0	0
T12	92774	0	0	0
T13	3062	10	0	0
T14	0	71	0	0
T16	161499	158	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	14	0	0
T20	82235	6	0	0
T23	5492	27	0	0
T50	0	2286	0	0
T58	1993	0	0	0
T62	0	19	0	0
T63	0	123	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	592707	0	0
T3	26056	69	0	0
T12	92774	0	0	0
T13	3062	10	0	0
T14	0	71	0	0
T16	161499	158	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	14	0	0
T20	82235	6	0	0
T23	5492	27	0	0
T50	0	2286	0	0
T58	1993	0	0	0
T62	0	19	0	0
T63	0	123	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T11 T82 
47         1/1                out_o.err <= '0;
           Tests:       T10 T11 T82 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T13 T16 T23 
50         1/1                out_o.err <= '0;
           Tests:       T13 T16 T23 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T13 T16 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T13 T16 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T13 T16 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T13 T16 
56         1/1                out_o.err <= '0;
           Tests:       T3 T13 T16 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T13 T16 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T13 T16 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T13 T16 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T82,T83,T76

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T16

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T16,T23

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T11,T82
0	0	1	-	-	Covered	T13,T16,T23
0	0	0	1	-	Covered	T3,T13,T16
0	0	0	0	1	Covered	T3,T13,T16
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	592648	0	0
UpdateCheck_A	375370398	592648	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	592648	0	0
T3	26056	68	0	0
T12	92774	0	0	0
T13	3062	10	0	0
T14	0	70	0	0
T16	161499	158	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	14	0	0
T20	82235	5	0	0
T23	5492	27	0	0
T50	0	2284	0	0
T58	1993	0	0	0
T62	0	19	0	0
T63	0	123	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	592648	0	0
T3	26056	68	0	0
T12	92774	0	0	0
T13	3062	10	0	0
T14	0	70	0	0
T16	161499	158	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	14	0	0
T20	82235	5	0	0
T23	5492	27	0	0
T50	0	2284	0	0
T58	1993	0	0	0
T62	0	19	0	0
T63	0	123	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T11 T82 
47         1/1                out_o.err <= '0;
           Tests:       T10 T11 T82 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T13 T16 T23 
50         1/1                out_o.err <= '0;
           Tests:       T13 T16 T23 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T13 T16 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T13 T16 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T13 T16 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T13 T16 
56         1/1                out_o.err <= '0;
           Tests:       T3 T13 T16 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T13 T16 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T13 T16 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T13 T16 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T82,T83,T76

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T16

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T16,T23

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T11,T82
0	0	1	-	-	Covered	T13,T16,T23
0	0	0	1	-	Covered	T3,T13,T16
0	0	0	0	1	Covered	T3,T13,T16
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	592553	0	0
UpdateCheck_A	375370398	592551	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	592553	0	0
T3	26056	68	0	0
T12	92774	0	0	0
T13	3062	10	0	0
T14	0	71	0	0
T16	161499	157	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	13	0	0
T20	82235	5	0	0
T23	5492	27	0	0
T50	0	2280	0	0
T58	1993	0	0	0
T62	0	18	0	0
T63	0	123	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	592551	0	0
T3	26056	68	0	0
T12	92774	0	0	0
T13	3062	10	0	0
T14	0	71	0	0
T16	161499	157	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	13	0	0
T20	82235	5	0	0
T23	5492	27	0	0
T50	0	2280	0	0
T58	1993	0	0	0
T62	0	18	0	0
T63	0	123	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T10 T11 T82 
47         1/1                out_o.err <= '0;
           Tests:       T10 T11 T82 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T13 T16 T23 
50         1/1                out_o.err <= '0;
           Tests:       T13 T16 T23 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T3 T13 T16 
53         1/1                out_o.part <= part_i;
           Tests:       T3 T13 T16 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T3 T13 T16 
55         1/1                out_o.attr <= Wip;
           Tests:       T3 T13 T16 
56         1/1                out_o.err <= '0;
           Tests:       T3 T13 T16 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T3 T13 T16 
59         1/1                out_o.attr <= Valid;
           Tests:       T3 T13 T16 
60         1/1                out_o.err <= err_i;
           Tests:       T3 T13 T16 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T82,T83,T76

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T16

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T16,T23

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T13,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T10,T11,T82
0	0	1	-	-	Covered	T13,T16,T23
0	0	0	1	-	Covered	T3,T13,T16
0	0	0	0	1	Covered	T3,T13,T16
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	375370398	591852	0	0
UpdateCheck_A	375370398	591851	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	591852	0	0
T3	26056	68	0	0
T12	92774	0	0	0
T13	3062	9	0	0
T14	0	71	0	0
T16	161499	143	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	13	0	0
T20	82235	5	0	0
T23	5492	23	0	0
T50	0	2278	0	0
T58	1993	0	0	0
T62	0	18	0	0
T63	0	122	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370398	591851	0	0
T3	26056	68	0	0
T12	92774	0	0	0
T13	3062	9	0	0
T14	0	71	0	0
T16	161499	143	0	0
T17	3581	0	0	0
T18	2390	0	0	0
T19	2298	13	0	0
T20	82235	5	0	0
T23	5492	23	0	0
T50	0	2278	0	0
T58	1993	0	0	0
T62	0	18	0	0
T63	0	122	0	0