Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.64 100.00 98.56 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.64 100.00 98.56 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_region_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.22 97.67 88.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_sw_sel

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_region_sel

Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00

27 // decode for software interface region 28 1/1 assign region_sel[0] = region_match[0]; Tests: T1 T2 T3  29 for (genvar i = 1; i < Regions; i++) begin: gen_region_priority 30 8/8 assign region_sel[i] = region_match[i] & ~|region_match[i-1:0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  31 end 32 33 // check for region match 34 always_comb begin 35 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_comps Tests: T1 T2 T3  36 1/1 region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size; Tests: T1 T2 T3  37 38 // region matches if address within range and if the partition matches 39 1/1 region_match[i] = addr_i >= region_attrs_i[i].cfg.base & Tests: T1 T2 T3  40 {1'b0, addr_i} < region_end[i] & 41 phase_i == region_attrs_i[i].phase & 42 mubi4_test_true_strict(region_attrs_i[i].cfg.en) & 43 req_i; 44 end 45 end 46 47 // select appropriate region configuration 48 always_comb begin 49 1/1 sel_cfg_o = '0; Tests: T1 T2 T3  50 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_sel Tests: T1 T2 T3  51 1/1 if (region_sel[i]) begin Tests: T1 T2 T3  52 1/1 sel_cfg_o = region_attrs_i[i].cfg; Tests: T1 T2 T3  53 end MISSING_ELSE

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_hw_sel

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00

27 // decode for software interface region 28 1/1 assign region_sel[0] = region_match[0]; Tests: T1 T2 T3  29 for (genvar i = 1; i < Regions; i++) begin: gen_region_priority 30 assign region_sel[i] = region_match[i] & ~|region_match[i-1:0]; 31 end 32 33 // check for region match 34 always_comb begin 35 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_comps Tests: T1 T2 T3  36 1/1 region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size; Tests: T1 T2 T3  37 38 // region matches if address within range and if the partition matches 39 1/1 region_match[i] = addr_i >= region_attrs_i[i].cfg.base & Tests: T1 T2 T3  40 {1'b0, addr_i} < region_end[i] & 41 phase_i == region_attrs_i[i].phase & 42 mubi4_test_true_strict(region_attrs_i[i].cfg.en) & 43 req_i; 44 end 45 end 46 47 // select appropriate region configuration 48 always_comb begin 49 1/1 sel_cfg_o = '0; Tests: T1 T2 T3  50 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_sel Tests: T1 T2 T3  51 1/1 if (region_sel[i]) begin Tests: T1 T2 T3  52 1/1 sel_cfg_o = region_attrs_i[i].cfg; Tests: T66 T113 T10  53 end MISSING_ELSE

Cond Coverage for Module : flash_mp_data_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T234,T275
11CoveredT63,T50,T28

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T143,T72
11CoveredT13,T14,T39

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T72,T159
11CoveredT65,T39,T26

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T39,T124
11CoveredT14,T50,T25

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T39,T26
11CoveredT50,T28,T10

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T72,T34
11CoveredT64,T86,T124

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T39,T86
11CoveredT14,T24,T26

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T13,T14
11CoveredT1,T3,T12

Branch Coverage for Module : flash_mp_data_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00


51 if (region_sel[i]) begin -1- 52 sel_cfg_o = region_attrs_i[i].cfg; ==> 53 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00

27 // decode for software interface region 28 1/1 assign region_sel[0] = region_match[0]; Tests: T1 T2 T3  29 for (genvar i = 1; i < Regions; i++) begin: gen_region_priority 30 8/8 assign region_sel[i] = region_match[i] & ~|region_match[i-1:0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  31 end 32 33 // check for region match 34 always_comb begin 35 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_comps Tests: T1 T2 T3  36 1/1 region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size; Tests: T1 T2 T3  37 38 // region matches if address within range and if the partition matches 39 1/1 region_match[i] = addr_i >= region_attrs_i[i].cfg.base & Tests: T1 T2 T3  40 {1'b0, addr_i} < region_end[i] & 41 phase_i == region_attrs_i[i].phase & 42 mubi4_test_true_strict(region_attrs_i[i].cfg.en) & 43 req_i; 44 end 45 end 46 47 // select appropriate region configuration 48 always_comb begin 49 1/1 sel_cfg_o = '0; Tests: T1 T2 T3  50 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_sel Tests: T1 T2 T3  51 1/1 if (region_sel[i]) begin Tests: T1 T2 T3  52 1/1 sel_cfg_o = region_attrs_i[i].cfg; Tests: T1 T3 T12  53 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T234,T275
11CoveredT63,T50,T8

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T143,T72
11CoveredT13,T14,T39

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T72,T159
11CoveredT65,T39,T26

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T39,T143
11CoveredT50,T39,T26

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T39,T26
11CoveredT50,T32,T239

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T72,T34
11CoveredT86,T32,T33

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T39,T86
11CoveredT14,T26,T86

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T14,T65
11CoveredT1,T3,T12

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00


51 if (region_sel[i]) begin -1- 52 sel_cfg_o = region_attrs_i[i].cfg; ==> 53 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T12
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00

27 // decode for software interface region 28 1/1 assign region_sel[0] = region_match[0]; Tests: T1 T2 T3  29 for (genvar i = 1; i < Regions; i++) begin: gen_region_priority 30 assign region_sel[i] = region_match[i] & ~|region_match[i-1:0]; 31 end 32 33 // check for region match 34 always_comb begin 35 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_comps Tests: T1 T2 T3  36 1/1 region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size; Tests: T1 T2 T3  37 38 // region matches if address within range and if the partition matches 39 1/1 region_match[i] = addr_i >= region_attrs_i[i].cfg.base & Tests: T1 T2 T3  40 {1'b0, addr_i} < region_end[i] & 41 phase_i == region_attrs_i[i].phase & 42 mubi4_test_true_strict(region_attrs_i[i].cfg.en) & 43 req_i; 44 end 45 end 46 47 // select appropriate region configuration 48 always_comb begin 49 1/1 sel_cfg_o = '0; Tests: T1 T2 T3  50 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_sel Tests: T1 T2 T3  51 1/1 if (region_sel[i]) begin Tests: T1 T2 T3  52 1/1 sel_cfg_o = region_attrs_i[i].cfg; Tests: T66 T113 T10  53 end MISSING_ELSE

Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00


51 if (region_sel[i]) begin -1- 52 sel_cfg_o = region_attrs_i[i].cfg; ==> 53 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T66,T113,T10
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00

27 // decode for software interface region 28 1/1 assign region_sel[0] = region_match[0]; Tests: T1 T2 T3  29 for (genvar i = 1; i < Regions; i++) begin: gen_region_priority 30 8/8 assign region_sel[i] = region_match[i] & ~|region_match[i-1:0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  31 end 32 33 // check for region match 34 always_comb begin 35 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_comps Tests: T1 T2 T3  36 1/1 region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size; Tests: T1 T2 T3  37 38 // region matches if address within range and if the partition matches 39 1/1 region_match[i] = addr_i >= region_attrs_i[i].cfg.base & Tests: T1 T2 T3  40 {1'b0, addr_i} < region_end[i] & 41 phase_i == region_attrs_i[i].phase & 42 mubi4_test_true_strict(region_attrs_i[i].cfg.en) & 43 req_i; 44 end 45 end 46 47 // select appropriate region configuration 48 always_comb begin 49 1/1 sel_cfg_o = '0; Tests: T1 T2 T3  50 1/1 for (int i = 0; i < Regions; i++) begin: gen_region_sel Tests: T1 T2 T3  51 1/1 if (region_sel[i]) begin Tests: T1 T2 T3  52 1/1 sel_cfg_o = region_attrs_i[i].cfg; Tests: T2 T3 T13  53 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T234,T275
11CoveredT28,T56,T68

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T234,T237
11CoveredT13,T86,T200

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T237,T276
11CoveredT86,T124,T45

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T124,T234
11CoveredT14,T25,T28

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T165,T234
11CoveredT28,T10,T33

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T277,T237
11CoveredT64,T86,T124

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T33,T277
11CoveredT24,T40,T86

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T13,T14
11CoveredT3,T13,T23

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00


51 if (region_sel[i]) begin -1- 52 sel_cfg_o = region_attrs_i[i].cfg; ==> 53 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T13
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%