Unified Coverage Report :: Module :: flash_ctrl_region_cfg

Module : flash_ctrl_region_cfg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.96	52.96

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_region_cfg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg	52.96	52.96

---

Module Instance : tb.dut.u_region_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.96	52.96

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.91	63.73				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg	100.00	100.00				100.00	100.00
gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg	90.00	70.00				100.00	100.00
gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg	91.11	73.33				100.00	100.00
gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg	100.00	100.00				100.00	100.00
gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg	90.00	70.00				100.00	100.00
gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg	91.11	73.33				100.00	100.00
u_lc_creator_seed_sw_rw_en_sync	100.00	100.00				100.00	100.00
u_lc_iso_part_sw_rd_en_sync	100.00	100.00				100.00	100.00
u_lc_iso_part_sw_wr_en_sync	100.00	100.00				100.00	100.00
u_lc_owner_seed_sw_rw_en_sync	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_region_cfg

	Line No.	Total	Covered	Percent
TOTAL		506	268	52.96
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
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CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	0	0.00
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CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	139	1	0	0.00
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CONT_ASSIGN	139	1	0	0.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
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CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	140	1	0	0.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	0	0.00
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CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	0	0.00
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CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	0	0.00
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CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
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CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
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CONT_ASSIGN	142	1	0	0.00
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CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
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CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
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CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
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CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
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CONT_ASSIGN	143	1	1	100.00
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CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	145	1	0	0.00

88                        for (genvar i = 0; i < NumBanks; i++) begin : gen_bank_cfg
89         2/2              assign bank_cfg_o[i].q = bank_cfg_i[i].q;
           Tests:       T1 T2 T3  | T1 T2 T3 
90                        end
91                      
92                        //////////////////////////////////////
93                        // Data partition regions
94                        //////////////////////////////////////
95                        // extra region is the default region
96                        for (genvar i = 0; i < MpRegions; i++) begin : gen_mp_regions
97         8/8              assign region_cfgs_o[i].base        = region_i[i].base.q;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
98         8/8              assign region_cfgs_o[i].size        = region_i[i].size.q;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
99         8/8              assign region_cfgs_o[i].en          = mubi4_t'(region_cfg_i[i].en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
100        8/8              assign region_cfgs_o[i].rd_en       = mubi4_t'(region_cfg_i[i].rd_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
101        8/8              assign region_cfgs_o[i].prog_en     = mubi4_t'(region_cfg_i[i].prog_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
102        8/8              assign region_cfgs_o[i].erase_en    = mubi4_t'(region_cfg_i[i].erase_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
103        8/8              assign region_cfgs_o[i].scramble_en = mubi4_t'(region_cfg_i[i].scramble_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
104        8/8              assign region_cfgs_o[i].ecc_en      = mubi4_t'(region_cfg_i[i].ecc_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
105        8/8              assign region_cfgs_o[i].he_en       = mubi4_t'(region_cfg_i[i].he_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
106                       end
107                     
108                       //default region
109                       assign region_cfgs_o[MpRegions].base        = '0;
110                       assign region_cfgs_o[MpRegions].size        = NumBanks * PagesPerBank;
111                       assign region_cfgs_o[MpRegions].en          = prim_mubi_pkg::MuBi4True;
112        1/1            assign region_cfgs_o[MpRegions].rd_en       = mubi4_t'(default_cfg_i.rd_en.q);
           Tests:       T1 T2 T3 
113        1/1            assign region_cfgs_o[MpRegions].prog_en     = mubi4_t'(default_cfg_i.prog_en.q);
           Tests:       T1 T2 T3 
114        1/1            assign region_cfgs_o[MpRegions].erase_en    = mubi4_t'(default_cfg_i.erase_en.q);
           Tests:       T1 T2 T3 
115        1/1            assign region_cfgs_o[MpRegions].scramble_en = mubi4_t'(default_cfg_i.scramble_en.q);
           Tests:       T1 T2 T3 
116        1/1            assign region_cfgs_o[MpRegions].ecc_en      = mubi4_t'(default_cfg_i.ecc_en.q);
           Tests:       T1 T2 T3 
117        1/1            assign region_cfgs_o[MpRegions].he_en       = mubi4_t'(default_cfg_i.he_en.q);
           Tests:       T1 T2 T3 
118                     
119                       //////////////////////////////////////
120                       // Info partition properties configuration
121                       //////////////////////////////////////
122                       sw_info_cfg_t   [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] sw_info_cfgs;
123                       info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_cfgs;
124                       localparam int InfoBits = $bits(sw_info_cfg_t) * InfosPerBank;
125                     
126                       // transform from unique names reg output to structure
127                       // Not all types have the maximum number of banks, so those are packed to 0
128        1/1            assign sw_info_cfgs[0][0] = InfoBits'(bank0_info0_cfg_i);
           Tests:       T1 T2 T3 
129        1/1            assign sw_info_cfgs[0][1] = InfoBits'(bank0_info1_cfg_i);
           Tests:       T1 T2 T3 
130        1/1            assign sw_info_cfgs[0][2] = InfoBits'(bank0_info2_cfg_i);
           Tests:       T1 T2 T3 
131        1/1            assign sw_info_cfgs[1][0] = InfoBits'(bank1_info0_cfg_i);
           Tests:       T1 T2 T3 
132        1/1            assign sw_info_cfgs[1][1] = InfoBits'(bank1_info1_cfg_i);
           Tests:       T1 T2 T3 
133        1/1            assign sw_info_cfgs[1][2] = InfoBits'(bank1_info2_cfg_i);
           Tests:       T1 T2 T3 
134                     
135                       // strip error indications
136                       for (genvar i = 0; i < NumBanks; i++) begin : gen_info_cfg_bank
137                         for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_cfg_type
138                           for (genvar k = 0; k < InfosPerBank; k++) begin : gen_info_cfg_page
139        26/60   ==>          assign info_cfgs[i][j][k].en          = mubi4_t'(sw_info_cfgs[i][j][k].en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
140        26/60   ==>          assign info_cfgs[i][j][k].rd_en       = mubi4_t'(sw_info_cfgs[i][j][k].rd_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
141        26/60   ==>          assign info_cfgs[i][j][k].prog_en     = mubi4_t'(sw_info_cfgs[i][j][k].prog_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
142        26/60   ==>          assign info_cfgs[i][j][k].erase_en    = mubi4_t'(sw_info_cfgs[i][j][k].erase_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
143        26/60   ==>          assign info_cfgs[i][j][k].scramble_en = mubi4_t'(sw_info_cfgs[i][j][k].scramble_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
144        26/60   ==>          assign info_cfgs[i][j][k].ecc_en      = mubi4_t'(sw_info_cfgs[i][j][k].ecc_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
145        26/60   ==>          assign info_cfgs[i][j][k].he_en       = mubi4_t'(sw_info_cfgs[i][j][k].he_en.q);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3