Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343923	1		T1	2		T2	2		T3	1
all_values[1]	343923	1		T1	2		T2	2		T3	1
all_values[2]	343923	1		T1	2		T2	2		T3	1
all_values[3]	343923	1		T1	2		T2	2		T3	1
all_values[4]	343923	1		T1	2		T2	2		T3	1
all_values[5]	343923	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	694356	1		T1	12		T2	12		T3	6
auto[1]	1369182	1		T27	6196		T36	6308		T37	11680

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1008049	1		T1	7		T2	7		T3	4
auto[1]	1055489	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	343768	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	155	1		T269	4		T275	2		T329	4
all_values[1]	auto[0]	auto[1]	343780	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	143	1		T269	8		T275	3		T329	3
all_values[2]	auto[0]	auto[0]	1639	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	50	1		T269	2		T275	1		T330	1
all_values[2]	auto[1]	auto[0]	342180	1		T27	1549		T36	1577		T37	2920
all_values[2]	auto[1]	auto[1]	54	1		T269	2		T275	2		T329	3
all_values[3]	auto[0]	auto[0]	1653	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	51	1		T269	2		T275	2		T329	1
all_values[3]	auto[1]	auto[0]	89335	1		T27	1549		T36	413		T28	1613
all_values[3]	auto[1]	auto[1]	252884	1		T36	1164		T37	2920		T38	1106
all_values[4]	auto[0]	auto[0]	1157	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	546	1		T1	1		T2	1		T17	1
all_values[4]	auto[1]	auto[0]	228319	1		T27	1		T36	995		T37	1460
all_values[4]	auto[1]	auto[1]	113901	1		T27	1548		T36	582		T37	1460
all_values[5]	auto[0]	auto[0]	1606	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	106	1		T39	1		T40	1		T41	1
all_values[5]	auto[1]	auto[0]	342160	1		T27	1549		T36	1577		T37	2920
all_values[5]	auto[1]	auto[1]	51	1		T269	1		T275	1		T330	2