Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	388255766	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	388255766	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	388255766	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	388255766	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	388255766	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	388255766	0	0	1052
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	388255766	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	388255766	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	388255766	0	0	1052
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	388255766	0	0	1052
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	388255766	0	0	1052
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	388255766	0	0	1052
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	388255766	0	0	1052
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	388255766	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	388255766	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	388255766	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	388255766	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	388255766	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	388255766	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	388255766	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	388255766	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1057	1057	0	0
tb.dut.FlashAddrKnown_A	0	0	388255766	271932921	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	388255766	387415641	0	0
tb.dut.FlashKnownO_A	0	0	388255766	387415641	0	0
tb.dut.FlashProgKnown_A	0	0	388255766	159099041	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	388255766	387415641	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	388255766	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	388255766	50	0	0
tb.dut.IntrErrO_A	0	0	388255766	387415641	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	388255766	387415641	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	388255766	387415641	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	388255766	387415641	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	388255766	387415641	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	388255766	387415641	0	0
tb.dut.MemRspPayLoad_A	0	0	388255766	5592021	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	388255766	387415641	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	388255766	387415641	0	0
tb.dut.MemTlDValidKnownO_A	0	0	388255766	387415641	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	388255766	387415641	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	388255766	387415641	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	388255766	387415641	0	0
tb.dut.RspPayLoad_A	0	0	388093290	44099560	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	388255766	387415641	0	0
tb.dut.TdoEnIsOne_A	0	0	388255766	387415641	0	0
tb.dut.TdoKnown_A	0	0	388255766	387415641	0	0
tb.dut.TlAReadyKnownO_A	0	0	388255766	387415641	0	0
tb.dut.TlDValidKnownO_A	0	0	388255766	387415641	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	390820167	4111	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	390820167	1870	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	390820167	2585	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	390820167	3086	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	390820167	3237	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	390820167	3101	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	390820167	3578	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	390820167	3596	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	390820167	3761	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	390820167	3767	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	390820167	3625	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	390820167	3831	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	390820167	1951	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	390820167	2315	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	390820167	1905	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	390820167	2337	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	390820167	919	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	390820167	907	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	390820167	1946	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	390820167	2196	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	390820167	2272	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	390820167	1880	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	390820167	3681	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	390820167	2312	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	390820167	2998	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	390820167	2923	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	390820167	1838	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	390820167	2376	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	390820167	3639	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	390820167	2623	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	390820167	3184	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	390820167	3105	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	390820167	3784	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	390820167	3647	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	390820167	3367	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	390820167	3736	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	390820167	3900	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	390820167	3469	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	390820167	1988	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	390820167	2350	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	390820167	1984	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	390820167	2443	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	390820167	1250	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	390820167	1857	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	390820167	1347	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	390820167	1826	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	390820167	2312	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	390820167	1758	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	390820167	3390	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	390820167	1836	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	390820167	3730	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	390820167	2949	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	390820167	1713	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	390820167	1880	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	390820167	2375	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	390820167	3411	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	390820167	2312	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	390820167	2143	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	390820167	1784	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	390820167	2723	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	390820167	3070	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	390820167	2137	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	390820167	2077	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	390820167	2541	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	390820167	1990	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	390820167	2591	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	390820167	2090	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	390820167	2135	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	390820167	2684	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	390820167	2631	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	390820167	3721	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	390820167	2710	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	390820167	3027	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	390820167	3598	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	390820167	3744	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	390820167	3202	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	390820167	3885	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	390820167	886	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	390820167	2319	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	390820167	2434	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	390820167	2329	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	390820167	2462	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	390820167	1392	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	390820167	2375	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	390820167	2270	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	390820167	2353	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	390820167	2398	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	388255766	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	388255766	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	388255766	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	388255766	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	388255766	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	388255766	24	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	390820040	32864270	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	390820040	389892701	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	390820040	389892701	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	390820040	44926096	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	390820040	389892701	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	390820040	389892701	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0
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tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0
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tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1267	1267	0	0

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