Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.23 95.68 93.90 98.31 92.52 98.21 96.89 98.12


Total tests in report: 1272
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.42 59.42 86.20 86.20 66.77 66.77 54.90 54.90 28.57 28.57 83.89 83.89 81.55 81.55 14.06 14.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.293659085
67.19 7.77 87.72 1.52 75.63 8.86 64.65 9.75 44.22 15.65 86.07 2.18 82.04 0.49 30.02 15.97 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.3353401679
72.60 5.40 90.67 2.95 81.16 5.52 66.90 2.25 44.22 0.00 91.59 5.53 90.19 8.16 43.43 13.41 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.319927000
77.73 5.13 92.68 2.01 82.61 1.46 78.40 11.50 57.14 12.93 92.83 1.24 90.39 0.19 50.03 6.60 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3733244241
81.05 3.32 92.84 0.16 83.05 0.44 78.40 0.00 62.59 5.44 93.07 0.23 90.87 0.49 66.52 16.49 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2054323887
83.26 2.21 93.44 0.60 83.36 0.30 82.52 4.13 72.11 9.52 93.77 0.70 90.97 0.10 66.65 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.3268829305
84.93 1.67 93.44 0.00 83.73 0.37 82.52 0.00 72.11 0.00 93.77 0.00 90.97 0.00 77.99 11.34 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.47123409
86.44 1.50 93.62 0.18 84.54 0.81 86.38 3.85 73.47 1.36 94.52 0.75 94.27 3.30 78.27 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3120992155
87.85 1.41 93.67 0.05 87.33 2.79 86.52 0.14 73.47 0.00 94.99 0.47 94.76 0.49 84.19 5.92 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2347577596
89.12 1.27 93.67 0.00 87.49 0.16 93.83 7.31 73.47 0.00 95.01 0.02 94.76 0.00 85.60 1.42 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.71327039
90.10 0.98 93.91 0.24 88.09 0.60 93.86 0.03 78.91 5.44 95.28 0.28 94.95 0.19 85.67 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.2261666604
90.63 0.54 93.92 0.01 88.18 0.10 94.09 0.22 82.31 3.40 95.28 0.00 94.95 0.00 85.70 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.859869906
91.15 0.51 94.91 0.99 88.60 0.42 94.31 0.22 82.31 0.00 97.12 1.83 94.95 0.00 85.82 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2481524803
91.58 0.44 94.98 0.07 88.81 0.21 94.64 0.32 82.31 0.00 97.29 0.17 94.95 0.00 88.10 2.28 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3062836039
92.02 0.43 95.00 0.02 88.86 0.05 94.83 0.19 85.03 2.72 97.33 0.04 94.95 0.00 88.10 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.4169231913
92.43 0.41 95.08 0.08 89.20 0.34 94.88 0.05 85.03 0.00 97.53 0.19 95.92 0.97 89.36 1.26 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3511982723
92.73 0.30 95.08 0.00 89.21 0.01 94.91 0.03 87.07 2.04 97.55 0.02 95.92 0.00 89.36 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.133322967
92.99 0.26 95.11 0.04 89.30 0.09 95.23 0.32 88.44 1.36 97.57 0.02 95.92 0.00 89.36 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.2832574753
93.25 0.26 95.23 0.12 89.31 0.01 95.23 0.00 88.44 0.00 97.57 0.00 95.92 0.00 91.03 1.66 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3188954223
93.44 0.19 95.24 0.01 89.37 0.07 95.26 0.03 88.44 0.00 97.59 0.02 95.92 0.00 92.26 1.23 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2933620669
93.63 0.18 95.36 0.12 90.06 0.69 95.74 0.48 88.44 0.00 97.59 0.00 95.92 0.00 92.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3508900836
93.79 0.16 95.43 0.06 90.21 0.15 95.84 0.10 89.12 0.68 97.72 0.13 95.92 0.00 92.29 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2855882787
93.95 0.16 95.43 0.00 90.68 0.47 95.84 0.00 89.12 0.00 97.76 0.04 96.02 0.10 92.79 0.49 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.1423661186
94.09 0.14 95.43 0.00 90.75 0.08 96.06 0.22 89.80 0.68 97.76 0.00 96.02 0.00 92.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1418486628
94.23 0.14 95.46 0.04 91.16 0.41 96.06 0.00 89.80 0.00 97.76 0.00 96.02 0.00 93.31 0.52 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2000005110
94.36 0.14 95.51 0.05 91.28 0.11 96.42 0.35 89.80 0.00 97.89 0.13 96.02 0.00 93.62 0.31 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.3266503852
94.49 0.13 95.54 0.03 91.48 0.20 96.66 0.24 89.80 0.00 97.95 0.06 96.02 0.00 93.99 0.37 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.371795572
94.61 0.12 95.64 0.10 91.58 0.10 97.12 0.47 89.80 0.00 97.95 0.00 96.02 0.00 94.17 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.951416499
94.73 0.11 95.64 0.00 91.64 0.06 97.12 0.00 90.48 0.68 97.97 0.02 96.02 0.00 94.20 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2071471917
94.83 0.11 95.64 0.00 91.65 0.01 97.19 0.06 91.16 0.68 97.97 0.00 96.02 0.00 94.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.1700721772
94.94 0.11 95.64 0.00 91.67 0.02 97.19 0.00 91.84 0.68 97.99 0.02 96.02 0.00 94.24 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1507646104
95.04 0.10 95.64 0.00 91.69 0.02 97.19 0.00 92.52 0.68 97.99 0.00 96.02 0.00 94.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.1407787112
95.13 0.09 95.64 0.00 92.29 0.60 97.19 0.00 92.52 0.00 97.99 0.00 96.02 0.00 94.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2520827968
95.21 0.08 95.64 0.00 92.41 0.12 97.25 0.06 92.52 0.00 97.99 0.00 96.02 0.00 94.61 0.37 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2600550880
95.28 0.07 95.64 0.00 92.49 0.08 97.25 0.00 92.52 0.00 97.99 0.00 96.31 0.29 94.76 0.15 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1268845160
95.34 0.06 95.64 0.00 92.49 0.00 97.25 0.00 92.52 0.00 97.99 0.00 96.70 0.39 94.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1398518249
95.38 0.05 95.64 0.00 92.53 0.05 97.48 0.22 92.52 0.00 98.02 0.02 96.70 0.00 94.79 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2412428598
95.43 0.05 95.64 0.00 92.54 0.01 97.48 0.00 92.52 0.00 98.02 0.00 96.70 0.00 95.10 0.31 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2705919513
95.47 0.04 95.64 0.00 92.57 0.03 97.48 0.00 92.52 0.00 98.02 0.00 96.70 0.00 95.38 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2017336852
95.51 0.04 95.64 0.00 92.61 0.04 97.53 0.05 92.52 0.00 98.02 0.00 96.70 0.00 95.56 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.3318940256
95.55 0.04 95.64 0.00 92.80 0.19 97.53 0.00 92.52 0.00 98.02 0.00 96.70 0.00 95.62 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3321500382
95.58 0.04 95.64 0.00 92.80 0.00 97.53 0.00 92.52 0.00 98.02 0.00 96.80 0.10 95.78 0.15 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4071551049
95.61 0.03 95.64 0.00 92.81 0.01 97.53 0.00 92.52 0.00 98.02 0.00 96.89 0.10 95.90 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3686475101
95.64 0.03 95.64 0.00 92.93 0.11 97.53 0.00 92.52 0.00 98.02 0.00 96.89 0.00 95.99 0.09 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1847807386
95.67 0.03 95.64 0.00 92.93 0.01 97.65 0.13 92.52 0.00 98.04 0.02 96.89 0.00 96.02 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2994978762
95.70 0.03 95.64 0.00 92.95 0.02 97.72 0.06 92.52 0.00 98.04 0.00 96.89 0.00 96.12 0.09 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1342880706
95.72 0.02 95.64 0.00 93.09 0.13 97.72 0.00 92.52 0.00 98.06 0.02 96.89 0.00 96.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.430519508
95.74 0.02 95.64 0.00 93.11 0.02 97.82 0.10 92.52 0.00 98.06 0.00 96.89 0.00 96.15 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1674305504
95.76 0.02 95.64 0.00 93.13 0.02 97.82 0.00 92.52 0.00 98.06 0.00 96.89 0.00 96.27 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.3029671973
95.78 0.02 95.64 0.00 93.13 0.01 97.94 0.13 92.52 0.00 98.06 0.00 96.89 0.00 96.27 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.41654886
95.80 0.02 95.64 0.00 93.14 0.01 97.94 0.00 92.52 0.00 98.06 0.00 96.89 0.00 96.39 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2901676564
95.82 0.02 95.64 0.00 93.14 0.00 98.07 0.13 92.52 0.00 98.06 0.00 96.89 0.00 96.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.43688489
95.84 0.02 95.64 0.00 93.23 0.09 98.07 0.00 92.52 0.00 98.10 0.04 96.89 0.00 96.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.3938093881
95.85 0.02 95.64 0.00 93.31 0.08 98.07 0.00 92.52 0.00 98.12 0.02 96.89 0.00 96.42 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1899025511
95.87 0.02 95.64 0.00 93.32 0.01 98.07 0.00 92.52 0.00 98.14 0.02 96.89 0.00 96.52 0.09 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3454554903
95.89 0.02 95.64 0.00 93.32 0.00 98.07 0.00 92.52 0.00 98.14 0.00 96.89 0.00 96.64 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.1837326634
95.91 0.02 95.64 0.00 93.32 0.00 98.07 0.00 92.52 0.00 98.14 0.00 96.89 0.00 96.76 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1406360484
95.92 0.02 95.64 0.00 93.32 0.00 98.07 0.00 92.52 0.00 98.14 0.00 96.89 0.00 96.89 0.12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.4240973231
95.94 0.01 95.64 0.00 93.33 0.01 98.10 0.03 92.52 0.00 98.14 0.00 96.89 0.00 96.95 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3216443301
95.95 0.01 95.64 0.00 93.33 0.00 98.17 0.06 92.52 0.00 98.14 0.00 96.89 0.00 96.98 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.685593555
95.97 0.01 95.64 0.00 93.33 0.00 98.17 0.00 92.52 0.00 98.14 0.00 96.89 0.00 97.07 0.09 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3894996548
95.98 0.01 95.68 0.04 93.33 0.00 98.19 0.02 92.52 0.00 98.14 0.00 96.89 0.00 97.10 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2133851167
95.99 0.01 95.68 0.00 93.35 0.03 98.19 0.00 92.52 0.00 98.14 0.00 96.89 0.00 97.16 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3964722915
96.00 0.01 95.68 0.00 93.44 0.09 98.19 0.00 92.52 0.00 98.14 0.00 96.89 0.00 97.16 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.646566273
96.01 0.01 95.68 0.00 93.49 0.05 98.19 0.00 92.52 0.00 98.14 0.00 96.89 0.00 97.19 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.3922235829
96.03 0.01 95.68 0.00 93.50 0.01 98.25 0.06 92.52 0.00 98.14 0.00 96.89 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2319662254
96.04 0.01 95.68 0.00 93.54 0.05 98.25 0.00 92.52 0.00 98.17 0.02 96.89 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.4197987480
96.04 0.01 95.68 0.00 93.54 0.00 98.31 0.06 92.52 0.00 98.17 0.00 96.89 0.00 97.19 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.1607024146
96.05 0.01 95.68 0.00 93.55 0.01 98.31 0.00 92.52 0.00 98.19 0.02 96.89 0.00 97.23 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.291927360
96.06 0.01 95.68 0.00 93.56 0.01 98.31 0.00 92.52 0.00 98.21 0.02 96.89 0.00 97.26 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.2659897113
96.07 0.01 95.68 0.00 93.56 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.32 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3291552450
96.08 0.01 95.68 0.00 93.56 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.38 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3295015207
96.09 0.01 95.68 0.00 93.56 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.44 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.3199630534
96.10 0.01 95.68 0.00 93.56 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.50 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.3498782107
96.11 0.01 95.68 0.00 93.56 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.56 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1521412736
96.11 0.01 95.68 0.00 93.56 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.63 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.3346568967
96.12 0.01 95.68 0.00 93.58 0.02 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.66 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.53639149
96.13 0.01 95.68 0.00 93.63 0.05 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.66 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.515786405
96.14 0.01 95.68 0.00 93.68 0.05 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.66 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.2703469323
96.14 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.69 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.59988607
96.14 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.72 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2539505956
96.15 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.3023207109
96.15 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2040002624
96.16 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.877978139
96.16 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.4082327974
96.17 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.530975042
96.17 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1189302390
96.18 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.775981748
96.18 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.3740490284
96.18 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.2126172558
96.19 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.237446155
96.19 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.1099005852
96.20 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.949531490
96.20 0.01 95.68 0.00 93.68 0.00 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.2782115432
96.21 0.01 95.68 0.00 93.71 0.03 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.442073973
96.21 0.01 95.68 0.00 93.73 0.02 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.131623759
96.21 0.01 95.68 0.00 93.74 0.02 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3966692533
96.21 0.01 95.68 0.00 93.76 0.02 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.254927383
96.22 0.01 95.68 0.00 93.78 0.02 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3181959967
96.22 0.01 95.68 0.00 93.80 0.02 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1871175905
96.22 0.01 95.68 0.00 93.81 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2089319319
96.22 0.01 95.68 0.00 93.82 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3163804197
96.22 0.01 95.68 0.00 93.83 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.594109401
96.22 0.01 95.68 0.00 93.84 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.1221355172
96.23 0.01 95.68 0.00 93.85 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2922909982
96.23 0.01 95.68 0.00 93.86 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.3155458852
96.23 0.01 95.68 0.00 93.87 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.666669589
96.23 0.01 95.68 0.00 93.88 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2275094146
96.23 0.01 95.68 0.00 93.89 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3465236146
96.23 0.01 95.68 0.00 93.90 0.01 98.31 0.00 92.52 0.00 98.21 0.00 96.89 0.00 98.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2544141464

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.250455337
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2269043965
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1020165537
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3603460639
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2140216089
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2416353343
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.305506136
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1082131814
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4197751404
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3844706550
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2163754736
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1625619075
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3325093909
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.494709394
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3039423933
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1252878927
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2840226727
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1223233630
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2886309505
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3975281747
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.223188396
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3807839332
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1144144385
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2375704132
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3113562116
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1312894572
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4063466482
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4009416629
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2682318271
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.776132368
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1019135602
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1419826119
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1822704583
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4031911786
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3641554348
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3780305234
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1656969265
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2107563147
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2713236570
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3609470243
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2235860547
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3298544017
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4077874542
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3383375961
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.579474471
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.534581677
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.102286409
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2116843729
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.377291344
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3590627388
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2619309092
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.607927492
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2347510973
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1258995677
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4099858655
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3633574992
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2375668223
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2314566389
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2627856922
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1554941321
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.1940123140
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.575893580
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2514540904
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1199586162
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.860288051
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2172337119
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2805732846
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1100578142
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1588284098
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1533856227
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.801561802
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.292230165
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1969097601
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2855575129
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1437839080
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3598556503
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1811775085
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.227380784
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2206147313
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/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.2473510860
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2409175913
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3252577059
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1404990072
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.677227506
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1599393965
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.2855061380
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.2405325907
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.2892477934
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.3321416172



Total test records in report: 1272
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2038521472 Aug 29 09:40:15 AM UTC 24 Aug 29 09:40:38 AM UTC 24 39860900 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.371795572 Aug 29 09:40:13 AM UTC 24 Aug 29 09:40:39 AM UTC 24 987400500 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3941450978 Aug 29 09:40:11 AM UTC 24 Aug 29 09:40:40 AM UTC 24 50993400 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.1731490308 Aug 29 09:40:15 AM UTC 24 Aug 29 09:40:42 AM UTC 24 33678800 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1119690730 Aug 29 09:40:15 AM UTC 24 Aug 29 09:40:42 AM UTC 24 122155300 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.1540892587 Aug 29 09:40:15 AM UTC 24 Aug 29 09:40:52 AM UTC 24 23062200 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.2074753704 Aug 29 09:40:11 AM UTC 24 Aug 29 09:41:00 AM UTC 24 41661500 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.293659085 Aug 29 09:40:25 AM UTC 24 Aug 29 09:41:02 AM UTC 24 70145100 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2539505956 Aug 29 09:40:31 AM UTC 24 Aug 29 09:41:11 AM UTC 24 10141300 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1654936065 Aug 29 09:40:43 AM UTC 24 Aug 29 09:41:13 AM UTC 24 127305400 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.3318940256 Aug 29 09:40:28 AM UTC 24 Aug 29 09:41:15 AM UTC 24 73020200 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1342880706 Aug 29 09:40:27 AM UTC 24 Aug 29 09:41:16 AM UTC 24 27083300 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.71327039 Aug 29 09:40:11 AM UTC 24 Aug 29 09:41:19 AM UTC 24 1472845600 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3733244241 Aug 29 09:40:54 AM UTC 24 Aug 29 09:41:21 AM UTC 24 84348000 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.1221355172 Aug 29 09:41:00 AM UTC 24 Aug 29 09:41:22 AM UTC 24 19564700 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1899025511 Aug 29 09:41:03 AM UTC 24 Aug 29 09:41:33 AM UTC 24 720082400 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.3353401679 Aug 29 09:40:15 AM UTC 24 Aug 29 09:41:36 AM UTC 24 10808637600 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2388306080 Aug 29 09:40:43 AM UTC 24 Aug 29 09:41:40 AM UTC 24 209508700 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.59988607 Aug 29 09:41:15 AM UTC 24 Aug 29 09:41:41 AM UTC 24 22580100 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3964722915 Aug 29 09:40:17 AM UTC 24 Aug 29 09:41:41 AM UTC 24 9384587200 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2481524803 Aug 29 09:41:12 AM UTC 24 Aug 29 09:41:41 AM UTC 24 19900400 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.1406152470 Aug 29 09:41:14 AM UTC 24 Aug 29 09:41:43 AM UTC 24 15291900 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.4292503575 Aug 29 09:40:15 AM UTC 24 Aug 29 09:41:43 AM UTC 24 2390981500 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.61732649 Aug 29 09:40:11 AM UTC 24 Aug 29 09:41:44 AM UTC 24 72510500 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.2659897113 Aug 29 09:41:22 AM UTC 24 Aug 29 09:41:47 AM UTC 24 45193600 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1819029427 Aug 29 09:41:19 AM UTC 24 Aug 29 09:41:49 AM UTC 24 26364800 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.1651704293 Aug 29 09:40:15 AM UTC 24 Aug 29 09:42:03 AM UTC 24 1299923200 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2296113221 Aug 29 09:41:01 AM UTC 24 Aug 29 09:42:04 AM UTC 24 658886900 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.951416499 Aug 29 09:41:40 AM UTC 24 Aug 29 09:42:07 AM UTC 24 71578700 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2460680352 Aug 29 09:40:15 AM UTC 24 Aug 29 09:42:09 AM UTC 24 1652212000 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2232478293 Aug 29 09:40:15 AM UTC 24 Aug 29 09:42:14 AM UTC 24 559549000 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3866063647 Aug 29 09:41:44 AM UTC 24 Aug 29 09:42:21 AM UTC 24 22044400 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.1625369065 Aug 29 09:40:40 AM UTC 24 Aug 29 09:42:31 AM UTC 24 1932621900 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3986805794 Aug 29 09:41:42 AM UTC 24 Aug 29 09:42:33 AM UTC 24 15333600 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.3841474442 Aug 29 09:41:37 AM UTC 24 Aug 29 09:42:33 AM UTC 24 27154900 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.1710764980 Aug 29 09:41:43 AM UTC 24 Aug 29 09:42:33 AM UTC 24 79191400 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.2698650148 Aug 29 09:40:17 AM UTC 24 Aug 29 09:42:43 AM UTC 24 2123700000 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.688961313 Aug 29 09:40:11 AM UTC 24 Aug 29 09:42:51 AM UTC 24 72115800 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2347577596 Aug 29 09:40:15 AM UTC 24 Aug 29 09:42:51 AM UTC 24 2506452200 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.4068482371 Aug 29 09:42:23 AM UTC 24 Aug 29 09:42:52 AM UTC 24 529449600 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.1352729140 Aug 29 09:40:11 AM UTC 24 Aug 29 09:43:00 AM UTC 24 3341229900 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2106301912 Aug 29 09:41:34 AM UTC 24 Aug 29 09:43:00 AM UTC 24 37156400 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2054323887 Aug 29 09:40:13 AM UTC 24 Aug 29 09:43:18 AM UTC 24 3734877900 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.2254312722 Aug 29 09:40:17 AM UTC 24 Aug 29 09:43:21 AM UTC 24 1379921400 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1470655131 Aug 29 09:40:22 AM UTC 24 Aug 29 09:43:31 AM UTC 24 1936719900 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2060500478 Aug 29 09:40:15 AM UTC 24 Aug 29 09:43:33 AM UTC 24 4979404500 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.3457495166 Aug 29 09:41:42 AM UTC 24 Aug 29 09:43:35 AM UTC 24 212417900 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.1149089172 Aug 29 09:43:01 AM UTC 24 Aug 29 09:43:38 AM UTC 24 75874000 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.595018293 Aug 29 09:40:17 AM UTC 24 Aug 29 09:43:48 AM UTC 24 726220700 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2187376104 Aug 29 09:40:17 AM UTC 24 Aug 29 09:43:49 AM UTC 24 2178637100 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.291927360 Aug 29 09:41:23 AM UTC 24 Aug 29 09:44:00 AM UTC 24 10011571800 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.4169231913 Aug 29 09:40:13 AM UTC 24 Aug 29 09:44:07 AM UTC 24 37639600 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.239831925 Aug 29 09:43:33 AM UTC 24 Aug 29 09:44:15 AM UTC 24 18232500 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.859869906 Aug 29 09:42:53 AM UTC 24 Aug 29 09:44:20 AM UTC 24 3431698000 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.3294738995 Aug 29 09:43:32 AM UTC 24 Aug 29 09:44:37 AM UTC 24 1323264200 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.2469068538 Aug 29 09:40:15 AM UTC 24 Aug 29 09:44:42 AM UTC 24 6907790300 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.4165306193 Aug 29 09:41:44 AM UTC 24 Aug 29 09:44:46 AM UTC 24 3341855600 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.1324375283 Aug 29 09:42:44 AM UTC 24 Aug 29 09:44:53 AM UTC 24 1015488200 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3508900836 Aug 29 09:41:50 AM UTC 24 Aug 29 09:44:55 AM UTC 24 1877773400 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.1696492227 Aug 29 09:42:54 AM UTC 24 Aug 29 09:44:56 AM UTC 24 525851700 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.1423661186 Aug 29 09:40:17 AM UTC 24 Aug 29 09:45:00 AM UTC 24 3516331100 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.3823938442 Aug 29 09:44:43 AM UTC 24 Aug 29 09:45:13 AM UTC 24 60263900 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3973503029 Aug 29 09:42:22 AM UTC 24 Aug 29 09:45:17 AM UTC 24 1880295100 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.3023207109 Aug 29 09:44:57 AM UTC 24 Aug 29 09:45:25 AM UTC 24 55413900 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1456274222 Aug 29 09:43:22 AM UTC 24 Aug 29 09:45:26 AM UTC 24 1961453000 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2040002624 Aug 29 09:44:46 AM UTC 24 Aug 29 09:45:37 AM UTC 24 40686200 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1790898803 Aug 29 09:44:54 AM UTC 24 Aug 29 09:45:38 AM UTC 24 28959200 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3062836039 Aug 29 09:40:20 AM UTC 24 Aug 29 09:45:43 AM UTC 24 22707848500 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3206477426 Aug 29 09:43:01 AM UTC 24 Aug 29 09:45:45 AM UTC 24 640971400 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.3306100882 Aug 29 09:42:54 AM UTC 24 Aug 29 09:45:46 AM UTC 24 3434356900 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2694151513 Aug 29 09:45:28 AM UTC 24 Aug 29 09:45:50 AM UTC 24 101607800 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.3980418160 Aug 29 09:45:29 AM UTC 24 Aug 29 09:45:52 AM UTC 24 305201700 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1745342989 Aug 29 09:44:56 AM UTC 24 Aug 29 09:45:53 AM UTC 24 165029700 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.2752718494 Aug 29 09:44:16 AM UTC 24 Aug 29 09:45:59 AM UTC 24 2474265700 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.3155458852 Aug 29 09:45:39 AM UTC 24 Aug 29 09:46:02 AM UTC 24 13856800 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1575426634 Aug 29 09:42:10 AM UTC 24 Aug 29 09:46:08 AM UTC 24 74427100 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.650925679 Aug 29 09:45:45 AM UTC 24 Aug 29 09:46:09 AM UTC 24 928784700 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.3369282368 Aug 29 09:45:29 AM UTC 24 Aug 29 09:46:11 AM UTC 24 112858200 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.681835856 Aug 29 09:45:47 AM UTC 24 Aug 29 09:46:13 AM UTC 24 40996500 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.3364394626 Aug 29 09:45:47 AM UTC 24 Aug 29 09:46:14 AM UTC 24 26321800 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.4029776856 Aug 29 09:45:51 AM UTC 24 Aug 29 09:46:20 AM UTC 24 33156200 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.4292360835 Aug 29 09:45:53 AM UTC 24 Aug 29 09:46:22 AM UTC 24 28149200 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3454554903 Aug 29 09:46:02 AM UTC 24 Aug 29 09:46:30 AM UTC 24 19196900 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.44167751 Aug 29 09:46:08 AM UTC 24 Aug 29 09:46:37 AM UTC 24 54672900 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2858187078 Aug 29 09:40:22 AM UTC 24 Aug 29 09:46:39 AM UTC 24 91012907600 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2901676564 Aug 29 09:45:39 AM UTC 24 Aug 29 09:46:43 AM UTC 24 362901400 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3325769922 Aug 29 09:43:35 AM UTC 24 Aug 29 09:46:44 AM UTC 24 650033500 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1176233659 Aug 29 09:45:14 AM UTC 24 Aug 29 09:46:58 AM UTC 24 5351139700 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.3928666912 Aug 29 09:46:04 AM UTC 24 Aug 29 09:46:59 AM UTC 24 182038200 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.328167427 Aug 29 09:46:12 AM UTC 24 Aug 29 09:46:59 AM UTC 24 46288600 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.68656208 Aug 29 09:52:58 AM UTC 24 Aug 29 09:54:52 AM UTC 24 1165880800 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.3017110482 Aug 29 09:46:15 AM UTC 24 Aug 29 09:47:01 AM UTC 24 26254000 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.985561024 Aug 29 09:44:08 AM UTC 24 Aug 29 09:47:18 AM UTC 24 1379550500 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2600550880 Aug 29 09:43:50 AM UTC 24 Aug 29 09:47:20 AM UTC 24 2311137400 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.780957423 Aug 29 09:43:19 AM UTC 24 Aug 29 09:47:31 AM UTC 24 11055211500 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.260415553 Aug 29 09:43:49 AM UTC 24 Aug 29 09:47:37 AM UTC 24 6791955100 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1881752450 Aug 29 09:47:01 AM UTC 24 Aug 29 09:47:39 AM UTC 24 416285400 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.64331102 Aug 29 09:43:40 AM UTC 24 Aug 29 09:47:55 AM UTC 24 5748907800 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.2161820428 Aug 29 09:47:40 AM UTC 24 Aug 29 09:48:21 AM UTC 24 46612500 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3988028647 Aug 29 09:40:17 AM UTC 24 Aug 29 09:48:23 AM UTC 24 3590455000 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3301682033 Aug 29 09:46:10 AM UTC 24 Aug 29 09:48:28 AM UTC 24 71426400 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3966692533 Aug 29 09:46:22 AM UTC 24 Aug 29 09:48:48 AM UTC 24 67308600 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.4011920852 Aug 29 09:47:19 AM UTC 24 Aug 29 09:48:57 AM UTC 24 6801214800 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.1723323146 Aug 29 09:48:22 AM UTC 24 Aug 29 09:49:02 AM UTC 24 57794800 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1367868482 Aug 29 09:46:24 AM UTC 24 Aug 29 09:49:10 AM UTC 24 741892500 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.461629469 Aug 29 09:44:21 AM UTC 24 Aug 29 09:49:12 AM UTC 24 11737596300 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.4065629409 Aug 29 09:48:20 AM UTC 24 Aug 29 09:49:21 AM UTC 24 1076061200 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.841035678 Aug 29 09:47:21 AM UTC 24 Aug 29 09:49:24 AM UTC 24 1278403300 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3976390285 Aug 29 09:46:44 AM UTC 24 Aug 29 09:49:33 AM UTC 24 82695000 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2855882787 Aug 29 09:46:02 AM UTC 24 Aug 29 09:49:42 AM UTC 24 10021968700 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1847807386 Aug 29 09:40:15 AM UTC 24 Aug 29 09:49:45 AM UTC 24 14622732200 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.1242562445 Aug 29 09:47:38 AM UTC 24 Aug 29 09:49:47 AM UTC 24 425174200 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.1790501147 Aug 29 09:48:12 AM UTC 24 Aug 29 09:49:50 AM UTC 24 608529900 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.392980507 Aug 29 09:44:38 AM UTC 24 Aug 29 09:49:52 AM UTC 24 23346368100 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.1482937913 Aug 29 09:49:34 AM UTC 24 Aug 29 09:50:03 AM UTC 24 21085500 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.1403853092 Aug 29 09:46:33 AM UTC 24 Aug 29 09:50:16 AM UTC 24 10962798500 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3291516388 Aug 29 09:49:49 AM UTC 24 Aug 29 09:50:34 AM UTC 24 20837300 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.1123299914 Aug 29 09:42:54 AM UTC 24 Aug 29 09:50:36 AM UTC 24 7319036700 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.4003689517 Aug 29 09:49:48 AM UTC 24 Aug 29 09:50:44 AM UTC 24 52966700 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.1166760623 Aug 29 09:47:56 AM UTC 24 Aug 29 09:50:46 AM UTC 24 1087823400 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.1681057393 Aug 29 09:50:17 AM UTC 24 Aug 29 09:50:47 AM UTC 24 221540700 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.184012663 Aug 29 09:49:48 AM UTC 24 Aug 29 09:50:48 AM UTC 24 63422300 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2925218203 Aug 29 09:49:13 AM UTC 24 Aug 29 09:50:50 AM UTC 24 4551331100 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.2812926101 Aug 29 09:40:11 AM UTC 24 Aug 29 09:50:51 AM UTC 24 4049297400 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3705660582 Aug 29 09:50:35 AM UTC 24 Aug 29 09:51:03 AM UTC 24 160432500 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.725313167 Aug 29 09:47:32 AM UTC 24 Aug 29 09:51:05 AM UTC 24 3060996000 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.362109564 Aug 29 09:41:48 AM UTC 24 Aug 29 09:51:05 AM UTC 24 7956880300 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.430519508 Aug 29 09:50:37 AM UTC 24 Aug 29 09:51:07 AM UTC 24 22655800 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3873402863 Aug 29 09:50:21 AM UTC 24 Aug 29 09:51:08 AM UTC 24 415199800 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.473970330 Aug 29 09:48:04 AM UTC 24 Aug 29 09:51:12 AM UTC 24 2592078700 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.587759175 Aug 29 09:50:51 AM UTC 24 Aug 29 09:51:15 AM UTC 24 71234600 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.4269351580 Aug 29 09:50:49 AM UTC 24 Aug 29 09:51:16 AM UTC 24 16521000 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.4197987480 Aug 29 09:50:48 AM UTC 24 Aug 29 09:51:16 AM UTC 24 58093000 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.2703469323 Aug 29 09:50:47 AM UTC 24 Aug 29 09:51:20 AM UTC 24 845804300 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.518017523 Aug 29 09:40:13 AM UTC 24 Aug 29 09:51:20 AM UTC 24 3488721900 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.4253340935 Aug 29 09:51:05 AM UTC 24 Aug 29 09:51:27 AM UTC 24 15886100 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.1267129700 Aug 29 09:51:03 AM UTC 24 Aug 29 09:51:29 AM UTC 24 48775500 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.3266503852 Aug 29 09:49:53 AM UTC 24 Aug 29 09:51:32 AM UTC 24 3504772200 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3654175268 Aug 29 09:50:45 AM UTC 24 Aug 29 09:51:37 AM UTC 24 1569936000 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.1067488910 Aug 29 09:51:09 AM UTC 24 Aug 29 09:51:39 AM UTC 24 322409600 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2497342497 Aug 29 09:51:08 AM UTC 24 Aug 29 09:51:46 AM UTC 24 27837600 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.666669589 Aug 29 09:48:24 AM UTC 24 Aug 29 09:51:59 AM UTC 24 12339369500 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.4039477941 Aug 29 09:51:16 AM UTC 24 Aug 29 09:52:06 AM UTC 24 110920800 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3164381593 Aug 29 09:51:17 AM UTC 24 Aug 29 09:52:07 AM UTC 24 43142300 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.1303000503 Aug 29 09:48:57 AM UTC 24 Aug 29 09:52:19 AM UTC 24 4121315400 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1268845160 Aug 29 09:46:59 AM UTC 24 Aug 29 09:52:30 AM UTC 24 11963201100 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.3883604787 Aug 29 09:51:21 AM UTC 24 Aug 29 09:52:34 AM UTC 24 87260500 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.578162267 Aug 29 09:49:22 AM UTC 24 Aug 29 09:52:37 AM UTC 24 8092441200 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.1373669037 Aug 29 09:49:11 AM UTC 24 Aug 29 09:52:43 AM UTC 24 1653421100 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.3938093881 Aug 29 09:52:07 AM UTC 24 Aug 29 09:52:57 AM UTC 24 1310816800 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.3481844897 Aug 29 09:48:29 AM UTC 24 Aug 29 09:52:57 AM UTC 24 1458009800 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.72304909 Aug 29 09:49:25 AM UTC 24 Aug 29 09:53:03 AM UTC 24 52470092900 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.3025004823 Aug 29 09:48:49 AM UTC 24 Aug 29 09:53:06 AM UTC 24 3422893100 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1312195954 Aug 29 09:51:06 AM UTC 24 Aug 29 09:53:44 AM UTC 24 10012267700 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.4277343392 Aug 29 09:53:07 AM UTC 24 Aug 29 09:53:47 AM UTC 24 22632100 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.3684869696 Aug 29 09:44:01 AM UTC 24 Aug 29 09:53:52 AM UTC 24 11931595400 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.432656992 Aug 29 09:52:38 AM UTC 24 Aug 29 09:54:16 AM UTC 24 1624787500 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.1147843281 Aug 29 09:51:21 AM UTC 24 Aug 29 09:54:38 AM UTC 24 1492382300 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1674305504 Aug 29 09:51:30 AM UTC 24 Aug 29 09:54:43 AM UTC 24 82389518300 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.1407787112 Aug 29 09:52:44 AM UTC 24 Aug 29 09:54:46 AM UTC 24 2671736900 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.4035222634 Aug 29 09:51:12 AM UTC 24 Aug 29 09:54:53 AM UTC 24 157745400 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.646566273 Aug 29 09:47:39 AM UTC 24 Aug 29 09:54:56 AM UTC 24 6318767000 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.4251157126 Aug 29 09:54:19 AM UTC 24 Aug 29 09:54:59 AM UTC 24 30982900 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.762310701 Aug 29 09:52:58 AM UTC 24 Aug 29 09:55:28 AM UTC 24 6573681900 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.2832574753 Aug 29 09:51:39 AM UTC 24 Aug 29 09:55:28 AM UTC 24 40193100 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.3268829305 Aug 29 09:40:13 AM UTC 24 Aug 29 09:55:34 AM UTC 24 40130207200 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.3588080972 Aug 29 09:53:54 AM UTC 24 Aug 29 09:55:39 AM UTC 24 1333171900 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.5739797 Aug 29 09:54:19 AM UTC 24 Aug 29 09:55:50 AM UTC 24 9570957500 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.3522545633 Aug 29 09:55:29 AM UTC 24 Aug 29 09:55:55 AM UTC 24 57362200 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.259466905 Aug 29 09:53:45 AM UTC 24 Aug 29 09:56:27 AM UTC 24 728792400 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3868341403 Aug 29 09:55:51 AM UTC 24 Aug 29 09:56:29 AM UTC 24 16346300 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.157973972 Aug 29 09:55:29 AM UTC 24 Aug 29 09:56:32 AM UTC 24 29186300 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.43688489 Aug 29 09:42:08 AM UTC 24 Aug 29 09:56:33 AM UTC 24 90159579200 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3095787443 Aug 29 09:49:03 AM UTC 24 Aug 29 09:56:39 AM UTC 24 3516514300 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.2261666604 Aug 29 09:42:04 AM UTC 24 Aug 29 09:56:45 AM UTC 24 67006662500 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.379467361 Aug 29 09:55:40 AM UTC 24 Aug 29 09:56:49 AM UTC 24 72432400 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1410796181 Aug 29 09:54:58 AM UTC 24 Aug 29 09:56:54 AM UTC 24 10678779100 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.2337257138 Aug 29 09:56:33 AM UTC 24 Aug 29 09:56:59 AM UTC 24 17342100 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.3265520139 Aug 29 09:56:38 AM UTC 24 Aug 29 09:57:06 AM UTC 24 829667700 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3181959967 Aug 29 09:56:40 AM UTC 24 Aug 29 09:57:09 AM UTC 24 14938800 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.254927383 Aug 29 09:56:46 AM UTC 24 Aug 29 09:57:11 AM UTC 24 16363400 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2638152758 Aug 29 09:56:50 AM UTC 24 Aug 29 09:57:15 AM UTC 24 186562800 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.395177821 Aug 29 09:54:37 AM UTC 24 Aug 29 09:57:16 AM UTC 24 2691266200 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2553254726 Aug 29 09:56:55 AM UTC 24 Aug 29 09:57:23 AM UTC 24 14912100 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.1944144170 Aug 29 09:57:00 AM UTC 24 Aug 29 09:57:23 AM UTC 24 25511600 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.2552854034 Aug 29 09:53:48 AM UTC 24 Aug 29 09:57:24 AM UTC 24 2283559100 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.1764253509 Aug 29 09:56:34 AM UTC 24 Aug 29 09:57:28 AM UTC 24 664536200 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.3724158038 Aug 29 09:57:09 AM UTC 24 Aug 29 09:57:38 AM UTC 24 33211700 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.1663277987 Aug 29 09:54:54 AM UTC 24 Aug 29 09:57:48 AM UTC 24 4524406000 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.2063598168 Aug 29 09:56:28 AM UTC 24 Aug 29 09:57:58 AM UTC 24 2598378500 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.864024350 Aug 29 09:46:32 AM UTC 24 Aug 29 09:57:59 AM UTC 24 741510700 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.511695404 Aug 29 09:57:23 AM UTC 24 Aug 29 09:58:01 AM UTC 24 30497900 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.3996959196 Aug 29 09:57:15 AM UTC 24 Aug 29 09:58:07 AM UTC 24 49087000 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.4158012883 Aug 29 09:54:47 AM UTC 24 Aug 29 09:58:14 AM UTC 24 5023139100 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.4108973843 Aug 29 09:46:38 AM UTC 24 Aug 29 09:58:15 AM UTC 24 2702401500 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3752643322 Aug 29 09:58:07 AM UTC 24 Aug 29 09:58:46 AM UTC 24 512259800 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.2905885385 Aug 29 09:51:17 AM UTC 24 Aug 29 09:58:46 AM UTC 24 3244608200 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1768803089 Aug 29 09:54:44 AM UTC 24 Aug 29 09:58:49 AM UTC 24 2728562600 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3075454182 Aug 29 09:57:07 AM UTC 24 Aug 29 09:58:49 AM UTC 24 10012426900 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3465236146 Aug 29 09:54:39 AM UTC 24 Aug 29 09:59:21 AM UTC 24 7430896800 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.470866617 Aug 29 09:41:17 AM UTC 24 Aug 29 09:59:30 AM UTC 24 200890508400 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2224765400 Aug 29 09:57:12 AM UTC 24 Aug 29 09:59:40 AM UTC 24 140452900 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.2578099710 Aug 29 09:53:04 AM UTC 24 Aug 29 09:59:51 AM UTC 24 6202872600 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.2544583095 Aug 29 09:57:25 AM UTC 24 Aug 29 10:00:00 AM UTC 24 802355100 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.3651579659 Aug 29 09:51:59 AM UTC 24 Aug 29 10:00:04 AM UTC 24 67072143100 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.463580763 Aug 29 09:59:41 AM UTC 24 Aug 29 10:00:16 AM UTC 24 52503800 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2319662254 Aug 29 09:40:13 AM UTC 24 Aug 29 10:00:26 AM UTC 24 338639800 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.4072622939 Aug 29 09:51:27 AM UTC 24 Aug 29 10:00:33 AM UTC 24 7190274800 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.4211780490 Aug 29 09:58:52 AM UTC 24 Aug 29 10:00:34 AM UTC 24 1237010300 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3464560047 Aug 29 09:55:00 AM UTC 24 Aug 29 10:00:36 AM UTC 24 13337307100 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1301342764 Aug 29 09:57:25 AM UTC 24 Aug 29 10:00:43 AM UTC 24 57168900 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.4268827394 Aug 29 09:58:52 AM UTC 24 Aug 29 10:00:43 AM UTC 24 4039484300 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.2301240615 Aug 29 09:42:34 AM UTC 24 Aug 29 10:01:07 AM UTC 24 1730602700 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.3693377026 Aug 29 09:58:04 AM UTC 24 Aug 29 10:01:08 AM UTC 24 9688546900 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.1355955798 Aug 29 10:00:07 AM UTC 24 Aug 29 10:01:09 AM UTC 24 1857388800 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.268119352 Aug 29 10:00:27 AM UTC 24 Aug 29 10:01:12 AM UTC 24 57939100 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.2444350793 Aug 29 09:59:22 AM UTC 24 Aug 29 10:01:21 AM UTC 24 1106422400 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.3906114218 Aug 29 10:00:16 AM UTC 24 Aug 29 10:01:21 AM UTC 24 541744600 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.2617841221 Aug 29 09:57:39 AM UTC 24 Aug 29 10:01:30 AM UTC 24 5664689500 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1859233411 Aug 29 09:58:00 AM UTC 24 Aug 29 10:01:32 AM UTC 24 349188600 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.1658303383 Aug 29 10:01:22 AM UTC 24 Aug 29 10:01:52 AM UTC 24 40948700 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.257222309 Aug 29 09:59:51 AM UTC 24 Aug 29 10:02:00 AM UTC 24 580024100 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3688049875 Aug 29 09:55:28 AM UTC 24 Aug 29 10:02:04 AM UTC 24 98490430500 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2274872560 Aug 29 09:46:15 AM UTC 24 Aug 29 10:02:04 AM UTC 24 15336279400 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1917112975 Aug 29 10:01:31 AM UTC 24 Aug 29 10:02:13 AM UTC 24 42893500 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.3005998190 Aug 29 10:01:22 AM UTC 24 Aug 29 10:02:14 AM UTC 24 70557300 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.1447869934 Aug 29 09:51:33 AM UTC 24 Aug 29 10:02:16 AM UTC 24 3082328400 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1857979093 Aug 29 09:58:52 AM UTC 24 Aug 29 10:02:22 AM UTC 24 2086420700 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.50872241 Aug 29 10:01:52 AM UTC 24 Aug 29 10:02:24 AM UTC 24 17829500 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.3455882948 Aug 29 10:01:32 AM UTC 24 Aug 29 10:02:39 AM UTC 24 291562400 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.2909161462 Aug 29 10:02:14 AM UTC 24 Aug 29 10:02:42 AM UTC 24 56672000 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.3519031728 Aug 29 10:01:09 AM UTC 24 Aug 29 10:02:42 AM UTC 24 1949527900 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1034776176 Aug 29 10:02:23 AM UTC 24 Aug 29 10:02:48 AM UTC 24 45719500 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2544141464 Aug 29 10:02:17 AM UTC 24 Aug 29 10:02:52 AM UTC 24 668625900 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2071471917 Aug 29 10:02:25 AM UTC 24 Aug 29 10:02:54 AM UTC 24 25318700 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.237446155 Aug 29 10:02:16 AM UTC 24 Aug 29 10:02:55 AM UTC 24 336050200 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2822221603 Aug 29 10:02:43 AM UTC 24 Aug 29 10:03:04 AM UTC 24 15911000 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2922909982 Aug 29 09:40:11 AM UTC 24 Aug 29 10:03:06 AM UTC 24 652266200 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1692194319 Aug 29 10:00:33 AM UTC 24 Aug 29 10:03:08 AM UTC 24 587366900 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3280229784 Aug 29 10:02:43 AM UTC 24 Aug 29 10:03:09 AM UTC 24 24677800 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.317635354 Aug 29 09:46:40 AM UTC 24 Aug 29 10:03:14 AM UTC 24 160184708100 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1881798932 Aug 29 10:02:40 AM UTC 24 Aug 29 10:03:10 AM UTC 24 20047700 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1816359885 Aug 29 10:02:52 AM UTC 24 Aug 29 10:03:15 AM UTC 24 113069300 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.255829874 Aug 29 10:00:00 AM UTC 24 Aug 29 10:03:29 AM UTC 24 2902621900 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.3210042232 Aug 29 10:02:05 AM UTC 24 Aug 29 10:03:30 AM UTC 24 14341294500 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.3058391763 Aug 29 10:03:11 AM UTC 24 Aug 29 10:03:37 AM UTC 24 198798200 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.610853302 Aug 29 10:00:44 AM UTC 24 Aug 29 10:03:37 AM UTC 24 2233865400 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1418486628 Aug 29 09:45:53 AM UTC 24 Aug 29 10:03:49 AM UTC 24 49714942900 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.3636061383 Aug 29 09:47:03 AM UTC 24 Aug 29 10:04:05 AM UTC 24 1147459600 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.3593174724 Aug 29 09:57:16 AM UTC 24 Aug 29 10:04:06 AM UTC 24 77161400 ps
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