Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	238890	1		T1	13		T2	37		T18	20
auto[FlashEraseBank]	269948	1		T2	6		T17	20		T20	4

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	265086	1		T2	43		T17	20		T18	20
auto[FlashOpProgram]	224066	1		T1	13		T12	1		T20	1
auto[FlashOpErase]	15686	1		T12	1		T23	16		T14	108
auto[FlashOpInvalid]	4000	1		T51	200		T216	200		T151	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	265086	1		T2	43		T17	20		T18	20
op[FlashOpProgram]	224066	1		T1	13		T12	1		T20	1
op[FlashOpErase]	15686	1		T12	1		T23	16		T14	108
read_erase_read	570	1		T23	14		T30	3		T74	2
read_prog_read	802	1		T20	1		T98	2		T59	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	368908	1		T1	13		T2	43		T17	20
auto[FlashPartInfo]	135560	1		T20	3		T7	1		T23	33
auto[FlashPartInfo1]	861	1		T39	1		T47	1		T55	1
auto[FlashPartInfo2]	3509	1		T20	3		T15	5		T27	8

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	194956	1		T2	43		T17	20		T18	20
auto[FlashPartData]	auto[FlashOpProgram]	166473	1		T1	13		T12	1		T7	1
auto[FlashPartData]	auto[FlashOpErase]	3575	1		T12	1		T23	6		T9	2
auto[FlashPartData]	auto[FlashOpInvalid]	3904	1		T51	198		T216	196		T151	198
auto[FlashPartInfo]	auto[FlashOpRead]	67424	1		T20	3		T7	1		T23	23
auto[FlashPartInfo]	auto[FlashOpProgram]	56000	1		T14	108		T8	3		T15	1
auto[FlashPartInfo]	auto[FlashOpErase]	12060	1		T23	10		T14	108		T51	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T51	2		T216	4		T151	2
auto[FlashPartInfo1]	auto[FlashOpRead]	676	1		T39	1		T47	1		T55	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	167	1		T154	1		T131	1		T157	32
auto[FlashPartInfo1]	auto[FlashOpErase]	8	1		T31	1		T150	1		T154	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	10	1		T154	2		T131	2		T134	2
auto[FlashPartInfo2]	auto[FlashOpRead]	2030	1		T20	2		T40	16		T47	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	1426	1		T20	1		T15	5		T27	8
auto[FlashPartInfo2]	auto[FlashOpErase]	43	1		T150	1		T149	1		T167	5
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T154	2		T131	2		T137	2