Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	2	30	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	2	30	93.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30981	1		T12	4		T14	220		T51	400
auto[1]	25	1		T20	1		T84	2		T349	4
auto[2]	40	1		T152	1		T178	12		T179	4
auto[3]	277	1		T23	18		T13	1		T26	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7847	1		T12	1		T23	5		T13	1
evic_idx[1]	7816	1		T12	1		T23	4		T14	55
evic_idx[2]	7828	1		T12	1		T23	4		T14	55
evic_idx[3]	7832	1		T12	1		T20	1		T23	5

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Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30447	1		T12	4		T23	18		T14	220
evic_op[2]	308	1		T20	1		T13	1		T59	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7549	1		T12	1		T14	55		T51	100
evic_idx[0]	evic_op[1]	auto[1]	3	1		T350	2		T351	1		-	-
evic_idx[0]	evic_op[1]	auto[2]	2	1		T352	1		T353	1		-	-
evic_idx[0]	evic_op[1]	auto[3]	64	1		T23	5		T149	2		T167	5
evic_idx[0]	evic_op[2]	auto[0]	65	1		T59	4		T80	1		T74	4
evic_idx[0]	evic_op[2]	auto[1]	5	1		T84	1		T349	1		T354	1
evic_idx[0]	evic_op[2]	auto[2]	6	1		T152	1		T355	1		T356	1
evic_idx[0]	evic_op[2]	auto[3]	11	1		T13	1		T357	1		T358	1
evic_idx[1]	evic_op[1]	auto[0]	7551	1		T12	1		T14	55		T51	100
evic_idx[1]	evic_op[1]	auto[1]	2	1		T350	1		T351	1		-	-
evic_idx[1]	evic_op[1]	auto[2]	1	1		T352	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	53	1		T23	4		T149	2		T167	3
evic_idx[1]	evic_op[2]	auto[0]	57	1		T59	4		T80	1		T74	4
evic_idx[1]	evic_op[2]	auto[1]	3	1		T84	1		T349	1		T359	1
evic_idx[1]	evic_op[2]	auto[2]	3	1		T360	1		T361	1		T362	1
evic_idx[1]	evic_op[2]	auto[3]	4	1		T363	1		T364	1		T365	1
evic_idx[2]	evic_op[1]	auto[0]	7550	1		T12	1		T14	55		T51	100
evic_idx[2]	evic_op[1]	auto[1]	4	1		T350	3		T351	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	56	1		T23	4		T149	3		T167	4
evic_idx[2]	evic_op[2]	auto[0]	59	1		T59	4		T80	1		T74	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T349	1		T366	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T361	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	14	1		T26	1		T97	1		T367	1
evic_idx[3]	evic_op[1]	auto[0]	7548	1		T12	1		T14	55		T51	100
evic_idx[3]	evic_op[1]	auto[1]	3	1		T350	2		T351	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	61	1		T23	5		T149	6		T167	5
evic_idx[3]	evic_op[2]	auto[0]	58	1		T59	4		T80	1		T74	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T20	1		T349	1		T368	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T355	1		T361	1		T369	1
evic_idx[3]	evic_op[2]	auto[3]	14	1		T370	1		T371	1		T372	1