Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	35908	1		T336	14793		T337	2738		T338	16108
rd_lvl[2]	42504	1		T339	1142		T336	10951		T340	541
rd_lvl[3]	4251	1		T339	448		T340	38		T341	81
rd_lvl[4]	31628	1		T339	85		T340	2		T342	5432
rd_lvl[5]	15328	1		T339	394		T340	2		T342	1148
rd_lvl[6]	11502	1		T36	564		T38	559		T343	2793
rd_lvl[7]	7093	1		T36	184		T38	200		T344	1151
rd_lvl[8]	18989	1		T37	2659		T38	32		T344	859
rd_lvl[9]	6678	1		T36	169		T37	261		T38	121
rd_lvl[10]	7096	1		T36	169		T38	121		T161	1062
rd_lvl[11]	2030	1		T160	330		T339	1		T35	331
rd_lvl[12]	10788	1		T177	1173		T160	449		T339	218
rd_lvl[13]	3758	1		T177	424		T345	220		T339	214
rd_lvl[14]	14707	1		T345	1687		T33	1592		T34	1160
rd_lvl[15]	2929	1		T34	375		T346	215		T347	411