Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343923	1		T1	2		T2	2		T3	1
all_pins[1]	343923	1		T1	2		T2	2		T3	1
all_pins[2]	343923	1		T1	2		T2	2		T3	1
all_pins[3]	343923	1		T1	2		T2	2		T3	1
all_pins[4]	343923	1		T1	2		T2	2		T3	1
all_pins[5]	343923	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1721048	1		T1	12		T2	12		T3	6
values[0x1]	342490	1		T27	1548		T36	1668		T37	4380
transitions[0x0=>0x1]	307858	1		T27	1548		T36	1499		T37	2920
transitions[0x1=>0x0]	307845	1		T27	1548		T36	1499		T37	2920

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	343768	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	155	1		T269	4		T275	2		T329	4
all_pins[0]	transitions[0x0=>0x1]	87	1		T275	1		T329	3		T330	4
all_pins[0]	transitions[0x1=>0x0]	75	1		T269	4		T275	2		T329	2
all_pins[1]	values[0x0]	343780	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	143	1		T269	8		T275	3		T329	3
all_pins[1]	transitions[0x0=>0x1]	121	1		T269	6		T275	3		T329	1
all_pins[1]	transitions[0x1=>0x0]	2630	1		T346	3		T373	1243		T374	35
all_pins[2]	values[0x0]	341271	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	2652	1		T346	3		T373	1243		T374	35
all_pins[2]	transitions[0x0=>0x1]	42	1		T269	2		T275	1		T329	2
all_pins[2]	transitions[0x1=>0x0]	215507	1		T36	1086		T37	2920		T38	1033
all_pins[3]	values[0x0]	125806	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	218117	1		T36	1086		T37	2920		T38	1033
all_pins[3]	transitions[0x0=>0x1]	186222	1		T36	917		T37	1460		T38	912
all_pins[3]	transitions[0x1=>0x0]	89477	1		T27	1548		T36	413		T28	1612
all_pins[4]	values[0x0]	222551	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	121372	1		T27	1548		T36	582		T37	1460
all_pins[4]	transitions[0x0=>0x1]	121363	1		T27	1548		T36	582		T37	1460
all_pins[4]	transitions[0x1=>0x0]	42	1		T269	1		T275	1		T330	2
all_pins[5]	values[0x0]	343872	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	51	1		T269	1		T275	1		T330	2
all_pins[5]	transitions[0x0=>0x1]	23	1		T275	1		T330	1		T332	1
all_pins[5]	transitions[0x1=>0x0]	114	1		T269	3		T275	2		T329	3