Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1		T269	7		T275	7		T329	7
all_values[1]	287	1		T269	7		T275	7		T329	7
all_values[2]	287	1		T269	7		T275	7		T329	7
all_values[3]	287	1		T269	7		T275	7		T329	7
all_values[4]	287	1		T269	7		T275	7		T329	7
all_values[5]	287	1		T269	7		T275	7		T329	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	949	1		T269	20		T275	19		T329	28
auto[1]	773	1		T269	22		T275	23		T329	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	571	1		T269	11		T275	11		T329	14
auto[1]	1151	1		T269	31		T275	31		T329	28

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1036	1		T269	21		T275	22		T329	22
auto[1]	686	1		T269	21		T275	20		T329	20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	103	1		T269	2		T275	4		T329	4
all_values[0]	auto[0]	auto[1]	auto[1]	85	1		T269	3		T275	2		T329	1
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T269	1		T329	1		T330	1
all_values[0]	auto[1]	auto[1]	auto[1]	43	1		T269	1		T275	1		T329	1
all_values[1]	auto[0]	auto[0]	auto[1]	105	1		T275	1		T329	2		T330	4
all_values[1]	auto[0]	auto[1]	auto[1]	63	1		T269	3		T275	2		T329	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T275	1		T329	1		T331	2
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T269	4		T275	3		T329	3
all_values[2]	auto[0]	auto[0]	auto[0]	90	1		T269	3		T275	2		T329	2
all_values[2]	auto[0]	auto[1]	auto[0]	93	1		T275	2		T329	2		T330	4
all_values[2]	auto[1]	auto[0]	auto[1]	61	1		T269	2		T275	1		T329	2
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T269	2		T275	2		T329	1
all_values[3]	auto[0]	auto[0]	auto[0]	99	1		T269	1		T275	2		T329	4
all_values[3]	auto[0]	auto[1]	auto[0]	75	1		T269	2		T275	1		T329	1
all_values[3]	auto[1]	auto[0]	auto[1]	55	1		T269	3		T275	2		T330	2
all_values[3]	auto[1]	auto[1]	auto[1]	58	1		T269	1		T275	2		T329	2
all_values[4]	auto[0]	auto[0]	auto[0]	48	1		T269	1		T275	1		T329	1
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T269	1		T275	1		T330	3
all_values[4]	auto[0]	auto[1]	auto[0]	54	1		T269	2		T275	2		T329	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1		T330	1		T331	1		T332	1
all_values[4]	auto[1]	auto[0]	auto[1]	77	1		T269	2		T275	1		T329	5
all_values[4]	auto[1]	auto[1]	auto[1]	52	1		T269	1		T275	2		T331	3
all_values[5]	auto[0]	auto[0]	auto[0]	59	1		T269	1		T329	2		T330	2
all_values[5]	auto[0]	auto[0]	auto[1]	31	1		T269	1		T275	1		T333	1
all_values[5]	auto[0]	auto[1]	auto[0]	53	1		T269	1		T275	1		T329	1
all_values[5]	auto[0]	auto[1]	auto[1]	22	1		T330	2		T334	1		T335	1
all_values[5]	auto[1]	auto[0]	auto[1]	68	1		T269	2		T275	2		T329	4
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T269	2		T275	3		T330	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal