FLASH_CTRL Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.575m	94.214us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	49.490s	49.087us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.026m	97.526us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	31.440s	407.559us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.314m	1.587ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.767m	2.891ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	36.230s	48.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	31.440s	407.559us	20	20	100.00
		flash_ctrl_csr_aliasing	1.767m	2.891ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	27.620s	28.416us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	27.490s	32.545us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	48.610s	43.142us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	3.251m	57.169us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.929m	147.890ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.228m	160.169ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.870s	40.822us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	55.511m	241.780ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	14.519m	67.007ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.067m	2.939ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.148h	108.589ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.237m	1.492ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.032m	29.111us	37	40	92.50
		flash_ctrl_rw_evict_all_en	1.024m	26.243us	39	40	97.50
		flash_ctrl_re_evict	1.116m	72.432us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	12.377m	3.094ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	12.377m	3.094ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.598m	25.433ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	48.580s	1.311ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.857m	1.364ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	52.218m	4.989ms	9	10	90.00
V2	error_prog_win	flash_ctrl_error_prog_win	26.623m	4.101ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	58.260m	3.611ms	4	5	80.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	28.460s	48.478us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.476m	2.179ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	45.060s	15.446us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.220s	51.632us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	40.303m	1.009ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.982m	29.052ms	50	50	100.00
		flash_ctrl_otp_reset	4.098m	40.382us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.929m	147.890ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.861m	27.495ms	38	40	95.00
		flash_ctrl_intr_wr	1.942m	5.786ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.232m	24.118ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.564m	111.840ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	2.106m	1.015ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.008m	1.278ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	43.360s	57.939us	5	5	100.00
		flash_ctrl_ro_derr	3.521m	12.339ms	10	10	100.00
		flash_ctrl_rw_derr	4.852m	1.984ms	10	10	100.00
		flash_ctrl_derr_detect	4.577m	3.211ms	5	5	100.00
		flash_ctrl_integrity	10.728m	25.391ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	40.120s	46.612us	5	5	100.00
		flash_ctrl_ro_serr	2.917m	4.038ms	10	10	100.00
		flash_ctrl_rw_serr	4.382m	6.908ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	2.021m	1.961ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.472m	9.571ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.943m	5.002ms	20	20	100.00
		flash_ctrl_write_word_sweep	21.570s	39.861us	1	1	100.00
		flash_ctrl_read_word_sweep	26.340s	122.155us	1	1	100.00
		flash_ctrl_ro	2.380m	2.102ms	20	20	100.00
		flash_ctrl_rw	10.761m	36.332ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	1.040m	362.901us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.012m	200.891ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	3.728m	10.020ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	29.540s	52.983us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	27.190s	38.741us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	38.340s	66.228us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	38.340s	66.228us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.026m	97.526us	5	5	100.00
		flash_ctrl_csr_rw	31.440s	407.559us	20	20	100.00
		flash_ctrl_csr_aliasing	1.767m	2.891ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	48.080s	63.059us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.026m	97.526us	5	5	100.00
		flash_ctrl_csr_rw	31.440s	407.559us	20	20	100.00
		flash_ctrl_csr_aliasing	1.767m	2.891ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	48.080s	63.059us	20	20	100.00
V2		TOTAL			1004	1013	99.11
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	28.950s	24.209us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	28.950s	24.209us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	28.950s	24.209us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	28.950s	24.209us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	31.200s	39.090us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
		flash_ctrl_tl_intg_err	21.143m	965.038us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	21.143m	965.038us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	21.143m	965.038us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	54.450s	209.509us	3	3	100.00
		flash_ctrl_wr_intg	25.870s	84.348us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.575m	94.214us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.098m	40.382us	80	80	100.00
		flash_ctrl_disable	45.060s	15.446us	50	50	100.00
		flash_ctrl_sec_info_access	2.285m	15.084ms	50	50	100.00
		flash_ctrl_connect	32.220s	51.632us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	29.040s	20.048us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	31.440s	407.559us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.950s	24.209us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	31.440s	407.559us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.950s	24.209us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	31.440s	407.559us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	28.950s	24.209us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	45.060s	15.446us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	54.450s	209.509us	3	3	100.00
		flash_ctrl_access_after_disable	28.370s	22.656us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	54.470s	27.155us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	45.060s	15.446us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	48.580s	1.311ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.761m	36.332ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.382m	6.908ms	10	10	100.00
		flash_ctrl_rw_derr	4.852m	1.984ms	10	10	100.00
		flash_ctrl_integrity	10.728m	25.391ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.929m	147.890ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	33.740s	668.626us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	27.530s	14.939us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	27.620s	25.319us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.120h	1.675ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.407m	37.156us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1272	1281	99.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.23	95.68	93.90	98.31	92.52	98.21	96.89	98.12

Failure Buckets

• Job timed out after * minutes has 3 failures:

  • Test flash_ctrl_error_mp has 1 failures.

    • 0.flash_ctrl_error_mp.67736258622676805556501546590478734322969024203482800725505775814129946475203
      Log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_error_prog_type has 1 failures.

    • 3.flash_ctrl_error_prog_type.37056817683788279191162945615738431178127287312934466218603678803543970206500
      Log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_rw has 1 failures.

    • 16.flash_ctrl_rw.25168765484920357119780041568543273779691797730645309371929280779010332027999
      Log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 3.flash_ctrl_rw_evict_all_en.17891620233462095631348395016998013790270995118689015407769020759930328588959
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 23413.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 23413.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_evict has 2 failures.

    • 5.flash_ctrl_rw_evict.86029493631482295432714012046681047628475496454330479452422700411835375923367
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 13676.9 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 13676.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.flash_ctrl_rw_evict.95923239693408408348076298919886685511799140585538663728099137628718379151689
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 23680.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 23680.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 2.flash_ctrl_rw_evict.91230304902927471991554613914461313627219927156312371672659035571205897732555
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 53776.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 53776.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp f8c5cbc7_d593ac12:ffffffff_d593ac* mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 15.flash_ctrl_intr_rd.5490926971519129207155570634646960290374003970002126015924311802902657020690
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 150358.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    f8c5cbc7_d593ac12:ffffffff_d593ac12  mismatch!!
        UVM_INFO @ 150358.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a_6ebddd52:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 32.flash_ctrl_intr_rd.99193283823750757036128409324292485578952755030352940662537421148733907493996
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 3948612.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    9088873a_6ebddd52:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 3948612.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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