Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	333142	1		T1	2		T2	1		T3	2
all_values[1]	333142	1		T1	2		T2	1		T3	2
all_values[2]	333142	1		T1	2		T2	1		T3	2
all_values[3]	333142	1		T1	2		T2	1		T3	2
all_values[4]	333142	1		T1	2		T2	1		T3	2
all_values[5]	333142	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	672625	1		T1	12		T2	6		T3	12
auto[1]	1326227	1		T30	5860		T39	31052		T31	5368

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	983153	1		T1	7		T2	4		T3	7
auto[1]	1015699	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	332985	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	157	1		T268	2		T269	7		T270	4
all_values[1]	auto[0]	auto[1]	333004	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	138	1		T268	3		T269	1		T270	4
all_values[2]	auto[0]	auto[0]	1601	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	50	1		T268	1		T270	1		T340	1
all_values[2]	auto[1]	auto[0]	331431	1		T30	1465		T39	7763		T31	1342
all_values[2]	auto[1]	auto[1]	60	1		T269	2		T270	2		T340	1
all_values[3]	auto[0]	auto[0]	1618	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	61	1		T269	1		T270	1		T340	1
all_values[3]	auto[1]	auto[0]	82545	1		T30	1465		T39	28		T31	1342
all_values[3]	auto[1]	auto[1]	248918	1		T39	7735		T35	598		T40	1648
all_values[4]	auto[0]	auto[0]	1140	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	512	1		T1	1		T3	1		T7	1
all_values[4]	auto[1]	auto[0]	231818	1		T30	1		T39	7154		T31	1
all_values[4]	auto[1]	auto[1]	99672	1		T30	1464		T39	609		T31	1341
all_values[5]	auto[0]	auto[0]	1567	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	87	1		T17	1		T25	1		T41	1
all_values[5]	auto[1]	auto[0]	331433	1		T30	1465		T39	7763		T31	1342
all_values[5]	auto[1]	auto[1]	55	1		T268	1		T270	2		T344	2