Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	387955770	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	387955770	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	387955770	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	387955770	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	387955770	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	387955770	0	0	1051
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	387955770	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	387955770	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	387955770	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	387955770	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	387955770	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	387955770	0	0	1051
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	387955770	0	0	1051
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	387955770	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	387955770	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	387955770	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	387955770	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	387955770	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	387955770	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	387955770	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	387955770	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1056	1056	0	0
tb.dut.FlashAddrKnown_A	0	0	387955770	264422591	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	387955770	387167133	0	0
tb.dut.FlashKnownO_A	0	0	387955770	387167133	0	0
tb.dut.FlashProgKnown_A	0	0	387955770	159864268	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	387955770	387167133	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	387955770	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	387955770	50	0	0
tb.dut.IntrErrO_A	0	0	387955770	387167133	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	387955770	387167133	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	387955770	387167133	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	387955770	387167133	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	387955770	387167133	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	387955770	387167133	0	0
tb.dut.MemRspPayLoad_A	0	0	387955770	5261662	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	387955770	387167133	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	387955770	387167133	0	0
tb.dut.MemTlDValidKnownO_A	0	0	387955770	387167133	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	387955770	387167133	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	387955770	387167133	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	387955770	387167133	0	0
tb.dut.RspPayLoad_A	0	0	387746155	39324318	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	387955770	387167133	0	0
tb.dut.TdoEnIsOne_A	0	0	387955770	387167133	0	0
tb.dut.TdoKnown_A	0	0	387955770	387167133	0	0
tb.dut.TlAReadyKnownO_A	0	0	387955770	387167133	0	0
tb.dut.TlDValidKnownO_A	0	0	387955770	387167133	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	390543779	5051	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	390543779	2715	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	390543779	3893	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	390543779	3990	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	390543779	4421	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	390543779	3886	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	390543779	3903	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	390543779	3568	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	390543779	4142	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	390543779	3537	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	390543779	4189	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	390543779	3954	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	390543779	2407	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	390543779	2845	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	390543779	2308	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	390543779	2385	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	390543779	2855	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	390543779	2647	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	390543779	2776	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	390543779	2476	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	390543779	3052	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	390543779	2034	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	390543779	4404	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	390543779	2643	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	390543779	3823	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	390543779	4155	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	390543779	2069	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	390543779	2376	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	390543779	3265	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	390543779	3563	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	390543779	2910	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	390543779	3919	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	390543779	4011	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	390543779	3710	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	390543779	3793	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	390543779	3600	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	390543779	2859	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	390543779	4356	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	390543779	2964	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	390543779	2044	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	390543779	2652	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	390543779	2829	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	390543779	2435	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	390543779	2945	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	390543779	2464	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	390543779	2853	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	390543779	2683	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	390543779	2702	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	390543779	3595	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	390543779	2739	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	390543779	3262	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	390543779	3697	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	390543779	2384	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	390543779	2916	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	390543779	2315	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	390543779	3687	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	390543779	2482	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	390543779	2685	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	390543779	2408	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	390543779	2107	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	390543779	3480	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	390543779	2299	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	390543779	2421	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	390543779	2941	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	390543779	2655	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	390543779	3242	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	390543779	2386	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	390543779	2348	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	390543779	3020	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	390543779	3803	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	390543779	3779	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	390543779	3617	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	390543779	3648	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	390543779	2997	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	390543779	3526	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	390543779	3887	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	390543779	3559	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	390543779	1930	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	390543779	2607	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	390543779	2252	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	390543779	2742	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	390543779	2448	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	390543779	2203	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	390543779	1836	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	390543779	2231	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	390543779	2073	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	390543779	2736	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	387955770	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	387955770	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	387955770	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	387955770	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	387955770	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	387955770	26	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	390543610	31110592	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	390543610	389674692	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	390543610	389674692	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	390543610	40224973	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	390543610	389674692	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	390543610	389674692	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
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tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
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tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1266	1266	0	0

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