| Name |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2609750584 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2080185500 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.495599376 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1038629747 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.315842050 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.941425912 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.719555499 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4236769203 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1169318586 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1701077385 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.68109369 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.209371500 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2866067514 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.211053221 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.936956806 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3276257371 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1612287518 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1440623666 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.598934148 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3051418210 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.4082408829 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3684139719 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1330386688 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2145089713 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.869772656 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2417133674 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3154748799 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4028281509 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1663712166 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3702168210 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3000171910 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1899284655 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2380820535 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.75381920 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2693620529 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.893645877 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1024842086 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4126573371 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2715361146 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1964978571 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.171806931 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1060223798 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2628464866 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3620027693 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3635445491 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.254688256 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4287213995 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2119109202 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2699825789 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3125883988 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1640676350 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2191004318 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3407929052 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4077975128 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.211865118 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.133603760 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.396666187 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1377190009 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.540702656 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4101613723 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.910866538 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1824779501 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2777811164 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1459339558 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.57723822 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1223655472 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2477614708 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.402519111 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1823560167 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1284969149 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3807762964 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.249805170 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1819674067 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1439977 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3940567771 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3453309308 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.910446854 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1887340321 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.377375420 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.938514416 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3972673667 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3854193085 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1208797996 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.358328072 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2623400669 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3620870949 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3699274539 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3323792856 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.232729949 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3175298195 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1601957863 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3053613884 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.463315866 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1511245328 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2772367586 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.27881549 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3718532087 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1905108274 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2682580807 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3196488486 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.937398490 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1602121579 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.2015143838 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3619256793 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.480734535 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.2903752901 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2286331498 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.3549097281 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3581256823 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.923995878 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.1965334862 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1415854029 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.87914622 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1464895294 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1631491773 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.1790610984 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3017474492 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2729471078 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.840036739 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.300981876 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.167121052 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3004556068 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4135196255 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1341875868 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2002800669 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.304394634 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.3388589449 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1324046264 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2326081158 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.784373640 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.838227618 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3522409441 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.209655012 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2388069631 |
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| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.767745785 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.1080567530 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2130076146 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.45474974 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.3058693587 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.190407319 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.3967624547 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1624582600 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.3115132636 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2627640949 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.4138436432 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2203202734 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.1691436077 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3207182655 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.3575700378 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3284833363 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.2068193685 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.3753039177 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.3091116727 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.357482645 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.1490215236 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.2425050471 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.2741302279 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3469194049 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.3196572527 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1790683594 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.1055675101 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.101511404 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3828488589 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.867926735 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.3361908518 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.2033735614 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2598677483 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1215371635 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3420930241 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2707746571 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2940768171 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2308351075 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.852387191 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3182295800 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.178586172 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.1143390978 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1597584623 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.1600898458 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.710062424 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1707083977 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1407740752 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4133376342 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.2599113699 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.2092257344 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2568469000 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2633939150 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.2956040018 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.3504889041 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2290998993 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.3273724498 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.1264588895 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.3078340301 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1361771311 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.2858272977 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1813558464 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.2154071609 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.433770605 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.883378517 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2346038515 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.2941405872 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1589160953 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.1487646181 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1477629631 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.2262622018 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.4101484843 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2608614879 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.660286970 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3678383710 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.663164461 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3447406320 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.1790160347 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3343890965 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.626494219 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.4122829500 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.2678946005 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2566590538 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1954267925 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.4181669583 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3035682262 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.2309976927 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.455584507 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.2969199555 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2768844100 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.3905727676 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1914215240 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.49058790 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3766430002 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.3969086974 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.1018312005 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.26133191 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1037792245 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.662147020 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1675938142 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.4199030885 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.1690941747 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.695862794 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3404741529 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.19713201 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1823734076 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1224609077 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.3824155176 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2622024707 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3686255341 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.2468146505 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1708791376 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1747980438 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.2683500074 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.419406153 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.696383439 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3644253402 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.377681009 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.46952372 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.144128637 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2168426794 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1358756153 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.2879277645 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3434037442 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2983842597 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.1758255602 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.1121076707 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3575117627 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1123408298 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2062496336 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.412608701 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.3920043186 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2705510058 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2211657745 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1185807102 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1480941123 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.2941438181 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3910387191 |
| /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1242084376 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1980133755 |
|
|
Sep 01 07:06:10 PM UTC 24 |
Sep 01 07:06:29 PM UTC 24 |
24843800 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.1115754573 |
|
|
Sep 01 07:05:59 PM UTC 24 |
Sep 01 07:06:35 PM UTC 24 |
16536500 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.569740575 |
|
|
Sep 01 07:06:01 PM UTC 24 |
Sep 01 07:06:36 PM UTC 24 |
54609300 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.615821292 |
|
|
Sep 01 07:06:10 PM UTC 24 |
Sep 01 07:06:38 PM UTC 24 |
278789200 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.2762499555 |
|
|
Sep 01 07:06:14 PM UTC 24 |
Sep 01 07:06:51 PM UTC 24 |
58174800 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1245367172 |
|
|
Sep 01 07:06:06 PM UTC 24 |
Sep 01 07:06:56 PM UTC 24 |
2299053300 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.2068816240 |
|
|
Sep 01 07:06:27 PM UTC 24 |
Sep 01 07:06:57 PM UTC 24 |
63792000 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2014761342 |
|
|
Sep 01 07:06:11 PM UTC 24 |
Sep 01 07:06:57 PM UTC 24 |
76285800 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3456595561 |
|
|
Sep 01 07:06:02 PM UTC 24 |
Sep 01 07:07:10 PM UTC 24 |
28361600 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2818055784 |
|
|
Sep 01 07:06:38 PM UTC 24 |
Sep 01 07:07:20 PM UTC 24 |
31619100 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1852287540 |
|
|
Sep 01 07:06:09 PM UTC 24 |
Sep 01 07:07:24 PM UTC 24 |
1791695100 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.3924526223 |
|
|
Sep 01 07:06:29 PM UTC 24 |
Sep 01 07:07:28 PM UTC 24 |
27115600 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.2267030587 |
|
|
Sep 01 07:06:58 PM UTC 24 |
Sep 01 07:07:29 PM UTC 24 |
16279400 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.2979197125 |
|
|
Sep 01 07:06:36 PM UTC 24 |
Sep 01 07:07:32 PM UTC 24 |
224055700 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1157768852 |
|
|
Sep 01 07:06:35 PM UTC 24 |
Sep 01 07:07:37 PM UTC 24 |
157257000 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1209128107 |
|
|
Sep 01 07:06:19 PM UTC 24 |
Sep 01 07:07:44 PM UTC 24 |
4196954300 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3773048166 |
|
|
Sep 01 07:07:11 PM UTC 24 |
Sep 01 07:07:44 PM UTC 24 |
46517000 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2899778561 |
|
|
Sep 01 07:06:13 PM UTC 24 |
Sep 01 07:07:48 PM UTC 24 |
701923700 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.3320393015 |
|
|
Sep 01 07:06:09 PM UTC 24 |
Sep 01 07:07:48 PM UTC 24 |
2146178300 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.3084276353 |
|
|
Sep 01 07:06:13 PM UTC 24 |
Sep 01 07:07:49 PM UTC 24 |
4752099300 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.124514430 |
|
|
Sep 01 07:07:22 PM UTC 24 |
Sep 01 07:07:50 PM UTC 24 |
17059500 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.3788076440 |
|
|
Sep 01 07:07:10 PM UTC 24 |
Sep 01 07:07:55 PM UTC 24 |
65598600 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2016294393 |
|
|
Sep 01 07:06:10 PM UTC 24 |
Sep 01 07:07:56 PM UTC 24 |
3543622400 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2121124538 |
|
|
Sep 01 07:07:29 PM UTC 24 |
Sep 01 07:07:57 PM UTC 24 |
26846100 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.848918927 |
|
|
Sep 01 07:07:34 PM UTC 24 |
Sep 01 07:08:01 PM UTC 24 |
20170700 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3262273266 |
|
|
Sep 01 07:07:30 PM UTC 24 |
Sep 01 07:08:02 PM UTC 24 |
15779100 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3881036565 |
|
|
Sep 01 07:07:24 PM UTC 24 |
Sep 01 07:08:07 PM UTC 24 |
646111700 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1521773243 |
|
|
Sep 01 07:07:45 PM UTC 24 |
Sep 01 07:08:14 PM UTC 24 |
15272100 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.4061981071 |
|
|
Sep 01 07:07:45 PM UTC 24 |
Sep 01 07:08:14 PM UTC 24 |
15531300 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.2708883075 |
|
|
Sep 01 07:06:04 PM UTC 24 |
Sep 01 07:08:17 PM UTC 24 |
6446414000 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2785459664 |
|
|
Sep 01 07:07:23 PM UTC 24 |
Sep 01 07:08:19 PM UTC 24 |
1183466600 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.3789532683 |
|
|
Sep 01 07:07:51 PM UTC 24 |
Sep 01 07:08:21 PM UTC 24 |
31818300 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.417175401 |
|
|
Sep 01 07:06:11 PM UTC 24 |
Sep 01 07:08:34 PM UTC 24 |
559305700 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.3879897807 |
|
|
Sep 01 07:06:04 PM UTC 24 |
Sep 01 07:08:36 PM UTC 24 |
268888900 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.1636767405 |
|
|
Sep 01 07:07:50 PM UTC 24 |
Sep 01 07:08:41 PM UTC 24 |
26711800 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3338765541 |
|
|
Sep 01 07:08:03 PM UTC 24 |
Sep 01 07:08:50 PM UTC 24 |
33286900 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.4268025580 |
|
|
Sep 01 07:08:03 PM UTC 24 |
Sep 01 07:08:51 PM UTC 24 |
21238600 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3043935165 |
|
|
Sep 01 07:07:56 PM UTC 24 |
Sep 01 07:08:53 PM UTC 24 |
17456100 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.680587488 |
|
|
Sep 01 07:06:16 PM UTC 24 |
Sep 01 07:08:53 PM UTC 24 |
944098600 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.37886208 |
|
|
Sep 01 07:07:49 PM UTC 24 |
Sep 01 07:08:59 PM UTC 24 |
156643200 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.1582360550 |
|
|
Sep 01 07:06:57 PM UTC 24 |
Sep 01 07:08:59 PM UTC 24 |
7540909700 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.2973270819 |
|
|
Sep 01 07:06:16 PM UTC 24 |
Sep 01 07:09:04 PM UTC 24 |
5573983200 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3984560594 |
|
|
Sep 01 07:06:14 PM UTC 24 |
Sep 01 07:09:17 PM UTC 24 |
706187800 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2486711963 |
|
|
Sep 01 07:06:06 PM UTC 24 |
Sep 01 07:09:19 PM UTC 24 |
1813517300 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.516954996 |
|
|
Sep 01 07:07:49 PM UTC 24 |
Sep 01 07:09:21 PM UTC 24 |
10019077500 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1295972276 |
|
|
Sep 01 07:08:50 PM UTC 24 |
Sep 01 07:09:21 PM UTC 24 |
3906642600 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2406231051 |
|
|
Sep 01 07:06:21 PM UTC 24 |
Sep 01 07:09:22 PM UTC 24 |
6128969400 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.2340635089 |
|
|
Sep 01 07:08:15 PM UTC 24 |
Sep 01 07:09:38 PM UTC 24 |
3133630600 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2685804694 |
|
|
Sep 01 07:06:09 PM UTC 24 |
Sep 01 07:09:45 PM UTC 24 |
1995191000 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1655971697 |
|
|
Sep 01 07:06:12 PM UTC 24 |
Sep 01 07:09:46 PM UTC 24 |
1228138400 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.2489468393 |
|
|
Sep 01 07:09:22 PM UTC 24 |
Sep 01 07:10:00 PM UTC 24 |
44028200 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2878449410 |
|
|
Sep 01 07:09:00 PM UTC 24 |
Sep 01 07:10:05 PM UTC 24 |
3351916000 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3702104373 |
|
|
Sep 01 07:06:18 PM UTC 24 |
Sep 01 07:10:11 PM UTC 24 |
1505663500 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2290807417 |
|
|
Sep 01 07:06:24 PM UTC 24 |
Sep 01 07:10:13 PM UTC 24 |
33983912500 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3953739029 |
|
|
Sep 01 07:06:16 PM UTC 24 |
Sep 01 07:10:27 PM UTC 24 |
1407856200 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.942158530 |
|
|
Sep 01 07:06:05 PM UTC 24 |
Sep 01 07:10:29 PM UTC 24 |
69577900 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.3297602196 |
|
|
Sep 01 07:09:53 PM UTC 24 |
Sep 01 07:10:40 PM UTC 24 |
31427000 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1194412889 |
|
|
Sep 01 07:09:45 PM UTC 24 |
Sep 01 07:10:46 PM UTC 24 |
1438287100 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3964112490 |
|
|
Sep 01 07:08:08 PM UTC 24 |
Sep 01 07:11:02 PM UTC 24 |
3685139900 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.537179742 |
|
|
Sep 01 07:08:35 PM UTC 24 |
Sep 01 07:11:14 PM UTC 24 |
278485800 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.1435068247 |
|
|
Sep 01 07:09:05 PM UTC 24 |
Sep 01 07:11:17 PM UTC 24 |
2558049900 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.1457395017 |
|
|
Sep 01 07:11:02 PM UTC 24 |
Sep 01 07:11:23 PM UTC 24 |
58241900 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.4241156459 |
|
|
Sep 01 07:07:55 PM UTC 24 |
Sep 01 07:11:32 PM UTC 24 |
20795300 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.2347954281 |
|
|
Sep 01 07:09:21 PM UTC 24 |
Sep 01 07:11:45 PM UTC 24 |
664223100 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2938213175 |
|
|
Sep 01 07:05:59 PM UTC 24 |
Sep 01 07:11:46 PM UTC 24 |
168372900 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1828615734 |
|
|
Sep 01 07:11:18 PM UTC 24 |
Sep 01 07:11:55 PM UTC 24 |
28530700 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.287745952 |
|
|
Sep 01 07:09:47 PM UTC 24 |
Sep 01 07:11:59 PM UTC 24 |
2480486600 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.998354074 |
|
|
Sep 01 07:09:18 PM UTC 24 |
Sep 01 07:12:04 PM UTC 24 |
4186409600 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.842360119 |
|
|
Sep 01 07:11:33 PM UTC 24 |
Sep 01 07:12:08 PM UTC 24 |
10550300 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.2321583850 |
|
|
Sep 01 07:09:23 PM UTC 24 |
Sep 01 07:12:11 PM UTC 24 |
615477100 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.1789117581 |
|
|
Sep 01 07:11:14 PM UTC 24 |
Sep 01 07:12:12 PM UTC 24 |
29288600 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.3942943527 |
|
|
Sep 01 07:12:00 PM UTC 24 |
Sep 01 07:12:23 PM UTC 24 |
25024900 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.265039820 |
|
|
Sep 01 07:10:43 PM UTC 24 |
Sep 01 07:12:24 PM UTC 24 |
1983392200 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.574899890 |
|
|
Sep 01 07:11:24 PM UTC 24 |
Sep 01 07:12:24 PM UTC 24 |
263319500 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.1447345664 |
|
|
Sep 01 07:12:09 PM UTC 24 |
Sep 01 07:12:37 PM UTC 24 |
85435400 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1740600244 |
|
|
Sep 01 07:12:12 PM UTC 24 |
Sep 01 07:12:42 PM UTC 24 |
23437200 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1578457493 |
|
|
Sep 01 07:12:25 PM UTC 24 |
Sep 01 07:12:51 PM UTC 24 |
45586300 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2839691246 |
|
|
Sep 01 07:12:25 PM UTC 24 |
Sep 01 07:12:55 PM UTC 24 |
45125600 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.527754097 |
|
|
Sep 01 07:12:24 PM UTC 24 |
Sep 01 07:12:57 PM UTC 24 |
827144000 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.1727885629 |
|
|
Sep 01 07:10:00 PM UTC 24 |
Sep 01 07:12:57 PM UTC 24 |
507818100 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2880127589 |
|
|
Sep 01 07:10:13 PM UTC 24 |
Sep 01 07:13:03 PM UTC 24 |
2288756700 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.1846562162 |
|
|
Sep 01 07:12:37 PM UTC 24 |
Sep 01 07:13:08 PM UTC 24 |
40752200 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1450015012 |
|
|
Sep 01 07:12:05 PM UTC 24 |
Sep 01 07:13:08 PM UTC 24 |
63788700 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.1101464534 |
|
|
Sep 01 07:12:13 PM UTC 24 |
Sep 01 07:13:14 PM UTC 24 |
5087297700 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3480575997 |
|
|
Sep 01 07:12:52 PM UTC 24 |
Sep 01 07:13:19 PM UTC 24 |
16088800 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.3971678115 |
|
|
Sep 01 07:13:04 PM UTC 24 |
Sep 01 07:13:25 PM UTC 24 |
31187700 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.672951566 |
|
|
Sep 01 07:12:57 PM UTC 24 |
Sep 01 07:13:26 PM UTC 24 |
29687000 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.56671216 |
|
|
Sep 01 07:06:04 PM UTC 24 |
Sep 01 07:13:27 PM UTC 24 |
2483273900 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.1128268273 |
|
|
Sep 01 07:10:06 PM UTC 24 |
Sep 01 07:13:34 PM UTC 24 |
6132590700 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1813591589 |
|
|
Sep 01 07:11:48 PM UTC 24 |
Sep 01 07:13:35 PM UTC 24 |
1548086400 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.3608419100 |
|
|
Sep 01 07:10:30 PM UTC 24 |
Sep 01 07:13:40 PM UTC 24 |
772177400 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.1299315417 |
|
|
Sep 01 07:12:58 PM UTC 24 |
Sep 01 07:13:45 PM UTC 24 |
27403800 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.546129083 |
|
|
Sep 01 07:06:04 PM UTC 24 |
Sep 01 07:13:56 PM UTC 24 |
96557600 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1570661117 |
|
|
Sep 01 07:09:39 PM UTC 24 |
Sep 01 07:13:59 PM UTC 24 |
2809961200 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.181149271 |
|
|
Sep 01 07:13:20 PM UTC 24 |
Sep 01 07:14:02 PM UTC 24 |
35177000 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.1133545095 |
|
|
Sep 01 07:13:09 PM UTC 24 |
Sep 01 07:14:03 PM UTC 24 |
55156300 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.3221382111 |
|
|
Sep 01 07:11:56 PM UTC 24 |
Sep 01 07:14:15 PM UTC 24 |
33074700 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2023007982 |
|
|
Sep 01 07:06:01 PM UTC 24 |
Sep 01 07:14:17 PM UTC 24 |
395263700 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2612688733 |
|
|
Sep 01 07:12:58 PM UTC 24 |
Sep 01 07:14:26 PM UTC 24 |
10048945500 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1649300863 |
|
|
Sep 01 07:14:03 PM UTC 24 |
Sep 01 07:14:41 PM UTC 24 |
975526200 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.719666466 |
|
|
Sep 01 07:13:36 PM UTC 24 |
Sep 01 07:14:48 PM UTC 24 |
1051461000 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2842915854 |
|
|
Sep 01 07:08:15 PM UTC 24 |
Sep 01 07:15:21 PM UTC 24 |
308815800 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3550123684 |
|
|
Sep 01 07:10:11 PM UTC 24 |
Sep 01 07:15:22 PM UTC 24 |
772652100 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.4142214768 |
|
|
Sep 01 07:13:09 PM UTC 24 |
Sep 01 07:15:26 PM UTC 24 |
112769700 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2705664816 |
|
|
Sep 01 07:14:29 PM UTC 24 |
Sep 01 07:15:34 PM UTC 24 |
8711646800 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3532135676 |
|
|
Sep 01 07:06:17 PM UTC 24 |
Sep 01 07:15:35 PM UTC 24 |
18171332400 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3150344300 |
|
|
Sep 01 07:15:02 PM UTC 24 |
Sep 01 07:15:43 PM UTC 24 |
80942800 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1995984796 |
|
|
Sep 01 07:13:27 PM UTC 24 |
Sep 01 07:15:43 PM UTC 24 |
733096900 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.1171286874 |
|
|
Sep 01 07:08:42 PM UTC 24 |
Sep 01 07:15:55 PM UTC 24 |
109800820100 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2011407696 |
|
|
Sep 01 07:15:35 PM UTC 24 |
Sep 01 07:16:18 PM UTC 24 |
33520100 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.475179002 |
|
|
Sep 01 07:13:26 PM UTC 24 |
Sep 01 07:16:30 PM UTC 24 |
242202400 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.3976323944 |
|
|
Sep 01 07:14:29 PM UTC 24 |
Sep 01 07:16:37 PM UTC 24 |
1653465700 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3576350271 |
|
|
Sep 01 07:15:26 PM UTC 24 |
Sep 01 07:16:57 PM UTC 24 |
1997519900 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3736980166 |
|
|
Sep 01 07:15:22 PM UTC 24 |
Sep 01 07:17:13 PM UTC 24 |
3417700900 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2832613415 |
|
|
Sep 01 07:10:44 PM UTC 24 |
Sep 01 07:17:18 PM UTC 24 |
12128080700 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1376194626 |
|
|
Sep 01 07:13:29 PM UTC 24 |
Sep 01 07:17:19 PM UTC 24 |
40981700 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.1607782307 |
|
|
Sep 01 07:13:46 PM UTC 24 |
Sep 01 07:17:19 PM UTC 24 |
139098600 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2932621744 |
|
|
Sep 01 07:10:47 PM UTC 24 |
Sep 01 07:17:29 PM UTC 24 |
155533680600 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.469835263 |
|
|
Sep 01 07:16:38 PM UTC 24 |
Sep 01 07:17:38 PM UTC 24 |
29209200 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.277228069 |
|
|
Sep 01 07:16:57 PM UTC 24 |
Sep 01 07:17:39 PM UTC 24 |
62047200 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.1356990407 |
|
|
Sep 01 07:16:48 PM UTC 24 |
Sep 01 07:17:42 PM UTC 24 |
55424300 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.601551033 |
|
|
Sep 01 07:17:20 PM UTC 24 |
Sep 01 07:17:42 PM UTC 24 |
24549900 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.825299953 |
|
|
Sep 01 07:16:21 PM UTC 24 |
Sep 01 07:17:45 PM UTC 24 |
1983222300 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.626183552 |
|
|
Sep 01 07:15:27 PM UTC 24 |
Sep 01 07:17:48 PM UTC 24 |
2990212100 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.2530613106 |
|
|
Sep 01 07:17:30 PM UTC 24 |
Sep 01 07:17:52 PM UTC 24 |
14413100 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.1849946704 |
|
|
Sep 01 07:17:05 PM UTC 24 |
Sep 01 07:17:52 PM UTC 24 |
30387900 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3678733625 |
|
|
Sep 01 07:14:46 PM UTC 24 |
Sep 01 07:17:53 PM UTC 24 |
12172225800 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2269505140 |
|
|
Sep 01 07:17:26 PM UTC 24 |
Sep 01 07:17:58 PM UTC 24 |
163688000 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.1218989441 |
|
|
Sep 01 07:17:25 PM UTC 24 |
Sep 01 07:18:02 PM UTC 24 |
86630500 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.3146923188 |
|
|
Sep 01 07:17:45 PM UTC 24 |
Sep 01 07:18:08 PM UTC 24 |
24175800 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.3849685559 |
|
|
Sep 01 07:17:42 PM UTC 24 |
Sep 01 07:18:11 PM UTC 24 |
111002300 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3788172522 |
|
|
Sep 01 07:17:53 PM UTC 24 |
Sep 01 07:18:13 PM UTC 24 |
45158200 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.37219457 |
|
|
Sep 01 07:17:47 PM UTC 24 |
Sep 01 07:18:14 PM UTC 24 |
26057700 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.2386454635 |
|
|
Sep 01 07:14:43 PM UTC 24 |
Sep 01 07:18:17 PM UTC 24 |
3582577100 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.3413529693 |
|
|
Sep 01 07:18:03 PM UTC 24 |
Sep 01 07:18:23 PM UTC 24 |
111823000 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.283083038 |
|
|
Sep 01 07:17:53 PM UTC 24 |
Sep 01 07:18:23 PM UTC 24 |
59254100 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.28383463 |
|
|
Sep 01 07:17:40 PM UTC 24 |
Sep 01 07:18:24 PM UTC 24 |
885175600 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.481049890 |
|
|
Sep 01 07:17:38 PM UTC 24 |
Sep 01 07:18:42 PM UTC 24 |
507335400 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.809443689 |
|
|
Sep 01 07:15:36 PM UTC 24 |
Sep 01 07:18:48 PM UTC 24 |
698033600 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.4223811434 |
|
|
Sep 01 07:18:18 PM UTC 24 |
Sep 01 07:18:52 PM UTC 24 |
19493200 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3989200533 |
|
|
Sep 01 07:15:23 PM UTC 24 |
Sep 01 07:18:56 PM UTC 24 |
1872510900 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.870132007 |
|
|
Sep 01 07:17:59 PM UTC 24 |
Sep 01 07:18:57 PM UTC 24 |
39989600 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.678294957 |
|
|
Sep 01 07:18:11 PM UTC 24 |
Sep 01 07:18:59 PM UTC 24 |
55653100 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.2743105037 |
|
|
Sep 01 07:17:19 PM UTC 24 |
Sep 01 07:19:05 PM UTC 24 |
3413838800 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1182932304 |
|
|
Sep 01 07:13:59 PM UTC 24 |
Sep 01 07:19:06 PM UTC 24 |
75779038000 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.2233463230 |
|
|
Sep 01 07:18:16 PM UTC 24 |
Sep 01 07:19:11 PM UTC 24 |
46006900 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3719724637 |
|
|
Sep 01 07:15:55 PM UTC 24 |
Sep 01 07:19:14 PM UTC 24 |
1676857900 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.3461676504 |
|
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Sep 01 07:18:58 PM UTC 24 |
Sep 01 07:19:33 PM UTC 24 |
333895500 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.2146257602 |
|
|
Sep 01 07:18:26 PM UTC 24 |
Sep 01 07:19:48 PM UTC 24 |
722786200 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.2002826287 |
|
|
Sep 01 07:15:45 PM UTC 24 |
Sep 01 07:19:48 PM UTC 24 |
3166794300 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.1495608782 |
|
|
Sep 01 07:15:44 PM UTC 24 |
Sep 01 07:20:06 PM UTC 24 |
2130205200 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.3340944127 |
|
|
Sep 01 07:19:11 PM UTC 24 |
Sep 01 07:20:14 PM UTC 24 |
9529610900 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3943065080 |
|
|
Sep 01 07:18:09 PM UTC 24 |
Sep 01 07:20:18 PM UTC 24 |
67109500 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2684168838 |
|
|
Sep 01 07:16:34 PM UTC 24 |
Sep 01 07:20:43 PM UTC 24 |
46222989300 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.533862140 |
|
|
Sep 01 07:16:36 PM UTC 24 |
Sep 01 07:20:46 PM UTC 24 |
9823399900 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.1335242751 |
|
|
Sep 01 07:20:07 PM UTC 24 |
Sep 01 07:20:52 PM UTC 24 |
344440400 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.862610532 |
|
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Sep 01 07:08:18 PM UTC 24 |
Sep 01 07:21:00 PM UTC 24 |
6423073600 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2337635222 |
|
|
Sep 01 07:17:55 PM UTC 24 |
Sep 01 07:21:18 PM UTC 24 |
10011652300 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.1842904331 |
|
|
Sep 01 07:20:53 PM UTC 24 |
Sep 01 07:21:32 PM UTC 24 |
32677600 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.4154564600 |
|
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Sep 01 07:19:14 PM UTC 24 |
Sep 01 07:21:35 PM UTC 24 |
827299200 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.275271014 |
|
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Sep 01 07:16:31 PM UTC 24 |
Sep 01 07:21:52 PM UTC 24 |
16226143000 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.838726023 |
|
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Sep 01 07:18:43 PM UTC 24 |
Sep 01 07:21:53 PM UTC 24 |
92452600 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1031090565 |
|
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Sep 01 07:20:47 PM UTC 24 |
Sep 01 07:22:03 PM UTC 24 |
2963383800 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.2300285293 |
|
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Sep 01 07:20:44 PM UTC 24 |
Sep 01 07:22:14 PM UTC 24 |
1901499300 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2457465830 |
|
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Sep 01 07:19:49 PM UTC 24 |
Sep 01 07:22:21 PM UTC 24 |
6844056800 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3656557361 |
|
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Sep 01 07:20:15 PM UTC 24 |
Sep 01 07:22:24 PM UTC 24 |
1058601300 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.1719717493 |
|
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Sep 01 07:22:25 PM UTC 24 |
Sep 01 07:22:50 PM UTC 24 |
189250500 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3243531056 |
|
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Sep 01 07:07:38 PM UTC 24 |
Sep 01 07:22:50 PM UTC 24 |
79918181100 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.3408433872 |
|
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Sep 01 07:18:24 PM UTC 24 |
Sep 01 07:22:52 PM UTC 24 |
2074795800 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.932787548 |
|
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Sep 01 07:18:24 PM UTC 24 |
Sep 01 07:22:58 PM UTC 24 |
1433148200 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.3618342800 |
|
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Sep 01 07:13:36 PM UTC 24 |
Sep 01 07:23:01 PM UTC 24 |
5395217200 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.2851063380 |
|
|
Sep 01 07:06:05 PM UTC 24 |
Sep 01 07:23:14 PM UTC 24 |
70135658300 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.3198537033 |
|
|
Sep 01 07:22:53 PM UTC 24 |
Sep 01 07:23:34 PM UTC 24 |
112581700 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.1991572807 |
|
|
Sep 01 07:22:51 PM UTC 24 |
Sep 01 07:23:35 PM UTC 24 |
78250800 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3323291054 |
|
|
Sep 01 07:22:59 PM UTC 24 |
Sep 01 07:23:36 PM UTC 24 |
17505200 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.6841370 |
|
|
Sep 01 07:22:03 PM UTC 24 |
Sep 01 07:23:44 PM UTC 24 |
4507839000 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.1905380369 |
|
|
Sep 01 07:22:51 PM UTC 24 |
Sep 01 07:23:47 PM UTC 24 |
30210700 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.363885894 |
|
|
Sep 01 07:21:01 PM UTC 24 |
Sep 01 07:23:55 PM UTC 24 |
4460011300 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3465803660 |
|
|
Sep 01 07:19:34 PM UTC 24 |
Sep 01 07:24:02 PM UTC 24 |
5606503600 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.239050533 |
|
|
Sep 01 07:23:37 PM UTC 24 |
Sep 01 07:24:08 PM UTC 24 |
21846100 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2251661039 |
|
|
Sep 01 07:18:27 PM UTC 24 |
Sep 01 07:24:08 PM UTC 24 |
102951300 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.862812967 |
|
|
Sep 01 07:16:11 PM UTC 24 |
Sep 01 07:24:08 PM UTC 24 |
15051637600 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.1025673416 |
|
|
Sep 01 07:23:48 PM UTC 24 |
Sep 01 07:24:15 PM UTC 24 |
15117600 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.3184149638 |
|
|
Sep 01 07:20:19 PM UTC 24 |
Sep 01 07:24:15 PM UTC 24 |
1773873000 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.596883167 |
|
|
Sep 01 07:24:02 PM UTC 24 |
Sep 01 07:24:20 PM UTC 24 |
21530900 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.2435722582 |
|
|
Sep 01 07:23:45 PM UTC 24 |
Sep 01 07:24:20 PM UTC 24 |
765872800 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1029453214 |
|
|
Sep 01 07:23:56 PM UTC 24 |
Sep 01 07:24:23 PM UTC 24 |
60565900 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3177461050 |
|
|
Sep 01 07:23:38 PM UTC 24 |
Sep 01 07:24:25 PM UTC 24 |
614195600 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2913433739 |
|
|
Sep 01 07:24:08 PM UTC 24 |
Sep 01 07:24:29 PM UTC 24 |
15681700 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.342202367 |
|
|
Sep 01 07:24:09 PM UTC 24 |
Sep 01 07:24:39 PM UTC 24 |
25350500 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.3947203780 |
|
|
Sep 01 07:24:15 PM UTC 24 |
Sep 01 07:24:40 PM UTC 24 |
86663900 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.599594671 |
|
|
Sep 01 07:23:14 PM UTC 24 |
Sep 01 07:24:45 PM UTC 24 |
2971365400 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3872329142 |
|
|
Sep 01 07:21:19 PM UTC 24 |
Sep 01 07:24:47 PM UTC 24 |
2318186800 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.3864131298 |
|
|
Sep 01 07:21:53 PM UTC 24 |
Sep 01 07:24:53 PM UTC 24 |
2412887500 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.2925998161 |
|
|
Sep 01 07:24:22 PM UTC 24 |
Sep 01 07:24:54 PM UTC 24 |
16812400 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.1515820544 |
|
|
Sep 01 07:24:24 PM UTC 24 |
Sep 01 07:24:56 PM UTC 24 |
38249000 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.455374234 |
|
|
Sep 01 07:14:49 PM UTC 24 |
Sep 01 07:25:19 PM UTC 24 |
43709857600 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4242669198 |
|
|
Sep 01 07:22:15 PM UTC 24 |
Sep 01 07:25:43 PM UTC 24 |
22428582900 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1730844654 |
|
|
Sep 01 07:24:57 PM UTC 24 |
Sep 01 07:25:43 PM UTC 24 |
444314000 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1217444812 |
|
|
Sep 01 07:24:24 PM UTC 24 |
Sep 01 07:25:48 PM UTC 24 |
32137200 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.1753772207 |
|
|
Sep 01 07:21:36 PM UTC 24 |
Sep 01 07:25:51 PM UTC 24 |
1320379600 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.692503565 |
|
|
Sep 01 07:24:40 PM UTC 24 |
Sep 01 07:25:59 PM UTC 24 |
725120100 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2492408241 |
|
|
Sep 01 07:18:53 PM UTC 24 |
Sep 01 07:26:32 PM UTC 24 |
5834520500 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.591708921 |
|
|
Sep 01 07:21:33 PM UTC 24 |
Sep 01 07:26:35 PM UTC 24 |
743686400 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3169203812 |
|
|
Sep 01 07:24:25 PM UTC 24 |
Sep 01 07:26:39 PM UTC 24 |
84835400 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.1587401421 |
|
|
Sep 01 07:24:15 PM UTC 24 |
Sep 01 07:26:49 PM UTC 24 |
30895600 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.4263071899 |
|
|
Sep 01 07:24:55 PM UTC 24 |
Sep 01 07:27:07 PM UTC 24 |
7489539700 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1464011766 |
|
|
Sep 01 07:26:37 PM UTC 24 |
Sep 01 07:27:18 PM UTC 24 |
46282900 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.2948557710 |
|
|
Sep 01 07:25:52 PM UTC 24 |
Sep 01 07:27:36 PM UTC 24 |
992260300 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3924345367 |
|
|
Sep 01 07:22:22 PM UTC 24 |
Sep 01 07:27:44 PM UTC 24 |
54677324400 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.837773640 |
|
|
Sep 01 07:08:22 PM UTC 24 |
Sep 01 07:27:47 PM UTC 24 |
80133591000 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.2102646846 |
|
|
Sep 01 07:25:52 PM UTC 24 |
Sep 01 07:27:54 PM UTC 24 |
3592520900 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.2986933291 |
|
|
Sep 01 07:24:47 PM UTC 24 |
Sep 01 07:28:01 PM UTC 24 |
139202000 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.2175815625 |
|
|
Sep 01 07:27:18 PM UTC 24 |
Sep 01 07:28:02 PM UTC 24 |
31148200 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2962585948 |
|
|
Sep 01 07:27:08 PM UTC 24 |
Sep 01 07:28:17 PM UTC 24 |
2362732500 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.1670813825 |
|
|
Sep 01 07:26:02 PM UTC 24 |
Sep 01 07:28:26 PM UTC 24 |
724542500 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.2430448321 |
|
|
Sep 01 07:26:58 PM UTC 24 |
Sep 01 07:28:43 PM UTC 24 |
1421447700 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.1596626519 |
|
|
Sep 01 07:13:43 PM UTC 24 |
Sep 01 07:28:47 PM UTC 24 |
50126242700 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.1163572717 |
|
|
Sep 01 07:28:33 PM UTC 24 |
Sep 01 07:29:04 PM UTC 24 |
32147400 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1729693458 |
|
|
Sep 01 07:26:00 PM UTC 24 |
Sep 01 07:29:11 PM UTC 24 |
3590603400 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3692421606 |
|
|
Sep 01 07:24:09 PM UTC 24 |
Sep 01 07:29:14 PM UTC 24 |
10015492300 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.2702289557 |
|
|
Sep 01 07:28:03 PM UTC 24 |
Sep 01 07:29:24 PM UTC 24 |
8604594400 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.2555777081 |
|
|
Sep 01 07:28:35 PM UTC 24 |
Sep 01 07:29:30 PM UTC 24 |
82042100 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.3598046031 |
|
|
Sep 01 07:28:44 PM UTC 24 |
Sep 01 07:29:35 PM UTC 24 |
30105900 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.517435851 |
|
|
Sep 01 07:19:49 PM UTC 24 |
Sep 01 07:29:37 PM UTC 24 |
3710980500 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1316861478 |
|
|
Sep 01 07:26:39 PM UTC 24 |
Sep 01 07:29:46 PM UTC 24 |
629739800 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.602941097 |
|
|
Sep 01 07:28:48 PM UTC 24 |
Sep 01 07:29:47 PM UTC 24 |
149108100 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.4143899973 |
|
|
Sep 01 07:08:54 PM UTC 24 |
Sep 01 07:29:51 PM UTC 24 |
621609600 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.1645141296 |
|
|
Sep 01 07:29:31 PM UTC 24 |
Sep 01 07:29:52 PM UTC 24 |
24428700 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.336362262 |
|
|
Sep 01 07:29:05 PM UTC 24 |
Sep 01 07:29:52 PM UTC 24 |
10546800 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2241411455 |
|
|
Sep 01 07:21:52 PM UTC 24 |
Sep 01 07:29:54 PM UTC 24 |
3972733700 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1876007336 |
|
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Sep 01 07:06:58 PM UTC 24 |
Sep 01 07:30:04 PM UTC 24 |
2391268100 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2680910801 |
|
|
Sep 01 07:29:38 PM UTC 24 |
Sep 01 07:30:07 PM UTC 24 |
919172300 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.102934237 |
|
|
Sep 01 07:29:47 PM UTC 24 |
Sep 01 07:30:07 PM UTC 24 |
15851200 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.918728744 |
|
|
Sep 01 07:29:48 PM UTC 24 |
Sep 01 07:30:15 PM UTC 24 |
16473200 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3383956960 |
|
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Sep 01 07:29:52 PM UTC 24 |
Sep 01 07:30:17 PM UTC 24 |
41173200 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.906361904 |
|
|
Sep 01 07:29:52 PM UTC 24 |
Sep 01 07:30:18 PM UTC 24 |
15259000 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.2153586955 |
|
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Sep 01 07:29:36 PM UTC 24 |
Sep 01 07:30:21 PM UTC 24 |
628489600 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2286015611 |
|
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Sep 01 07:29:53 PM UTC 24 |
Sep 01 07:30:21 PM UTC 24 |
46692000 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.2225741909 |
|
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Sep 01 07:27:22 PM UTC 24 |
Sep 01 07:30:24 PM UTC 24 |
817255200 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1864368579 |
|
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Sep 01 07:29:57 PM UTC 24 |
Sep 01 07:30:25 PM UTC 24 |
596093400 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2183352419 |
|
|
Sep 01 07:29:14 PM UTC 24 |
Sep 01 07:30:28 PM UTC 24 |
1191177300 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.4005450590 |
|
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Sep 01 07:26:51 PM UTC 24 |
Sep 01 07:30:33 PM UTC 24 |
1143024800 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.597175622 |
|
|
Sep 01 07:30:21 PM UTC 24 |
Sep 01 07:30:52 PM UTC 24 |
432702000 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1813753271 |
|
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Sep 01 07:28:01 PM UTC 24 |
Sep 01 07:30:53 PM UTC 24 |
2443385000 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3626711165 |
|
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Sep 01 07:29:54 PM UTC 24 |
Sep 01 07:30:57 PM UTC 24 |
10031521700 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2734296337 |
|
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Sep 01 07:27:48 PM UTC 24 |
Sep 01 07:31:08 PM UTC 24 |
5641694900 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.230931277 |
|
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Sep 01 07:30:05 PM UTC 24 |
Sep 01 07:31:17 PM UTC 24 |
27177800 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.967244267 |
|
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Sep 01 07:27:37 PM UTC 24 |
Sep 01 07:31:25 PM UTC 24 |
5377280300 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3707855308 |
|
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Sep 01 07:27:45 PM UTC 24 |
Sep 01 07:31:28 PM UTC 24 |
4208102400 ps |