Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	228855	1		T1	20		T3	4		T18	20
auto[FlashEraseBank]	262479	1		T7	14		T14	17		T19	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	248543	1		T1	20		T3	2		T18	20
auto[FlashOpProgram]	224206	1		T3	1		T7	14		T19	1
auto[FlashOpErase]	14585	1		T3	1		T15	41		T27	16
auto[FlashOpInvalid]	4000	1		T22	200		T89	200		T154	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	248543	1		T1	20		T3	2		T18	20
op[FlashOpProgram]	224206	1		T3	1		T7	14		T19	1
op[FlashOpErase]	14585	1		T3	1		T15	41		T27	16
read_erase_read	557	1		T27	12		T10	1		T63	2
read_prog_read	841	1		T16	1		T28	5		T59	4

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	352754	1		T1	20		T3	4		T7	14
auto[FlashPartInfo]	134109	1		T26	4		T27	26		T28	14
auto[FlashPartInfo1]	847	1		T17	1		T41	4		T57	2
auto[FlashPartInfo2]	3624	1		T8	1		T27	5		T28	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	177012	1		T1	20		T3	2		T18	20
auto[FlashPartData]	auto[FlashOpProgram]	168262	1		T3	1		T7	14		T19	1
auto[FlashPartData]	auto[FlashOpErase]	3570	1		T3	1		T15	41		T27	9
auto[FlashPartData]	auto[FlashOpInvalid]	3910	1		T22	198		T89	192		T154	196
auto[FlashPartInfo]	auto[FlashOpRead]	68780	1		T26	4		T27	21		T28	11
auto[FlashPartInfo]	auto[FlashOpProgram]	54288	1		T28	3		T30	225		T9	2
auto[FlashPartInfo]	auto[FlashOpErase]	10967	1		T27	5		T22	1		T52	191
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T22	2		T89	8		T154	4
auto[FlashPartInfo1]	auto[FlashOpRead]	678	1		T17	1		T41	4		T57	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T133	1		T135	32		T137	32
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T157	2		T133	1		T139	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T133	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2073	1		T27	3		T28	2		T59	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	1494	1		T8	1		T30	12		T9	1
auto[FlashPartInfo2]	auto[FlashOpErase]	43	1		T27	2		T151	2		T155	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T172	2		T421	2		T133	2