Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28439	1		T3	4		T16	8		T15	1
auto[1]	59	1		T26	1		T151	2		T231	4
auto[2]	34	1		T28	1		T151	6		T74	4
auto[3]	312	1		T27	10		T28	1		T107	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7212	1		T3	1		T16	2		T27	2
evic_idx[1]	7210	1		T3	1		T16	2		T27	4
evic_idx[2]	7208	1		T3	1		T16	2		T26	1
evic_idx[3]	7214	1		T3	1		T16	2		T15	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28075	1		T3	4		T15	1		T27	10
evic_op[2]	297	1		T16	8		T26	1		T28	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6938	1		T3	1		T22	100		T52	92
evic_idx[0]	evic_op[1]	auto[1]	11	1		T155	2		T171	2		T227	1
evic_idx[0]	evic_op[1]	auto[2]	4	1		T151	3		T422	1		-	-
evic_idx[0]	evic_op[1]	auto[3]	68	1		T27	2		T151	3		T155	3
evic_idx[0]	evic_op[2]	auto[0]	55	1		T16	2		T63	4		T251	1
evic_idx[0]	evic_op[2]	auto[1]	5	1		T231	1		T423	1		T424	1
evic_idx[0]	evic_op[2]	auto[2]	7	1		T319	1		T425	1		T426	1
evic_idx[0]	evic_op[2]	auto[3]	6	1		T28	1		T427	1		T428	1
evic_idx[1]	evic_op[1]	auto[0]	6939	1		T3	1		T22	100		T52	92
evic_idx[1]	evic_op[1]	auto[1]	7	1		T171	1		T227	2		T429	1
evic_idx[1]	evic_op[1]	auto[2]	1	1		T422	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	75	1		T27	4		T151	3		T155	1
evic_idx[1]	evic_op[2]	auto[0]	55	1		T16	2		T63	4		T251	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T231	1		T319	1		T430	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T425	1		T431	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	9	1		T325	1		T432	1		T433	1
evic_idx[2]	evic_op[1]	auto[0]	6936	1		T3	1		T22	100		T52	92
evic_idx[2]	evic_op[1]	auto[1]	9	1		T171	1		T227	1		T429	4
evic_idx[2]	evic_op[1]	auto[2]	3	1		T151	2		T422	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	67	1		T27	4		T151	2		T155	1
evic_idx[2]	evic_op[2]	auto[0]	58	1		T16	2		T63	4		T251	1
evic_idx[2]	evic_op[2]	auto[1]	9	1		T26	1		T231	1		T42	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T434	1		T431	1		T435	1
evic_idx[2]	evic_op[2]	auto[3]	5	1		T436	1		T426	1		T437	1
evic_idx[3]	evic_op[1]	auto[0]	6938	1		T3	1		T15	1		T22	100
evic_idx[3]	evic_op[1]	auto[1]	11	1		T151	2		T171	1		T227	1
evic_idx[3]	evic_op[1]	auto[2]	2	1		T151	1		T422	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	66	1		T151	1		T155	3		T171	1
evic_idx[3]	evic_op[2]	auto[0]	56	1		T16	2		T63	4		T251	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T231	1		T430	1		T438	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T28	1		T439	1		T440	1
evic_idx[3]	evic_op[2]	auto[3]	16	1		T107	1		T425	1		T325	1