Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	39906	1		T39	2506		T345	1045		T346	16192
rd_lvl[2]	53635	1		T39	1216		T345	254		T346	12112
rd_lvl[3]	8636	1		T39	518		T347	285		T345	1
rd_lvl[4]	22721	1		T39	460		T347	81		T348	2619
rd_lvl[5]	16379	1		T39	392		T348	1396		T349	553
rd_lvl[6]	9820	1		T39	15		T347	2		T348	919
rd_lvl[7]	6595	1		T39	358		T350	322		T348	309
rd_lvl[8]	8491	1		T39	352		T350	93		T38	826
rd_lvl[9]	6013	1		T39	549		T213	491		T350	50
rd_lvl[10]	5345	1		T39	152		T213	1233		T350	47
rd_lvl[11]	3182	1		T38	12		T349	169		T345	1
rd_lvl[12]	4384	1		T40	1340		T332	1159		T351	58
rd_lvl[13]	3870	1		T40	308		T347	1		T352	77
rd_lvl[14]	12802	1		T35	294		T37	284		T345	1
rd_lvl[15]	4727	1		T35	180		T37	145		T353	163