Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	333142	1		T1	2		T2	1		T3	2
all_pins[1]	333142	1		T1	2		T2	1		T3	2
all_pins[2]	333142	1		T1	2		T2	1		T3	2
all_pins[3]	333142	1		T1	2		T2	1		T3	2
all_pins[4]	333142	1		T1	2		T2	1		T3	2
all_pins[5]	333142	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1670720	1		T1	12		T2	6		T3	12
values[0x1]	328132	1		T30	1464		T39	7158		T31	1341
transitions[0x0=>0x1]	294202	1		T30	1464		T39	6546		T31	1341
transitions[0x1=>0x0]	294186	1		T30	1464		T39	6546		T31	1341

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	332985	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	157	1		T268	2		T269	7		T270	4
all_pins[0]	transitions[0x0=>0x1]	98	1		T268	1		T269	7		T270	3
all_pins[0]	transitions[0x1=>0x0]	79	1		T268	2		T269	1		T270	3
all_pins[1]	values[0x0]	333004	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	138	1		T268	3		T269	1		T270	4
all_pins[1]	transitions[0x0=>0x1]	110	1		T268	3		T269	1		T270	3
all_pins[1]	transitions[0x1=>0x0]	4696	1		T35	124		T37	120		T353	167
all_pins[2]	values[0x0]	328418	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	4724	1		T35	124		T37	120		T353	167
all_pins[2]	transitions[0x0=>0x1]	46	1		T269	1		T270	2		T340	1
all_pins[2]	transitions[0x1=>0x0]	206735	1		T39	6518		T35	474		T40	1648
all_pins[3]	values[0x0]	121729	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	211413	1		T39	6518		T35	598		T40	1648
all_pins[3]	transitions[0x0=>0x1]	182298	1		T39	5906		T35	474		T40	1648
all_pins[3]	transitions[0x1=>0x0]	82530	1		T30	1464		T39	28		T31	1341
all_pins[4]	values[0x0]	221497	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	111645	1		T30	1464		T39	640		T31	1341
all_pins[4]	transitions[0x0=>0x1]	111629	1		T30	1464		T39	640		T31	1341
all_pins[4]	transitions[0x1=>0x0]	39	1		T268	1		T270	1		T344	1
all_pins[5]	values[0x0]	333087	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	55	1		T268	1		T270	2		T344	2
all_pins[5]	transitions[0x0=>0x1]	21	1		T344	1		T355	2		T356	1
all_pins[5]	transitions[0x1=>0x0]	107	1		T268	1		T269	6		T270	2