Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T268	4		T269	7		T270	7
all_values[1]	275	1		T268	4		T269	7		T270	7
all_values[2]	275	1		T268	4		T269	7		T270	7
all_values[3]	275	1		T268	4		T269	7		T270	7
all_values[4]	275	1		T268	4		T269	7		T270	7
all_values[5]	275	1		T268	4		T269	7		T270	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	879	1		T268	13		T269	22		T270	20
auto[1]	771	1		T268	11		T269	20		T270	22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	563	1		T268	13		T269	11		T270	15
auto[1]	1087	1		T268	11		T269	31		T270	27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	993	1		T268	18		T269	20		T270	25
auto[1]	657	1		T268	6		T269	22		T270	17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	86	1		T268	1		T270	1		T340	1
all_values[0]	auto[0]	auto[1]	auto[1]	74	1		T268	1		T269	1		T270	4
all_values[0]	auto[1]	auto[0]	auto[1]	61	1		T268	1		T269	2		T270	2
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T268	1		T269	4		T340	1
all_values[1]	auto[0]	auto[0]	auto[1]	103	1		T268	2		T269	5		T270	1
all_values[1]	auto[0]	auto[1]	auto[1]	70	1		T268	1		T270	2		T340	1
all_values[1]	auto[1]	auto[0]	auto[1]	54	1		T268	1		T269	1		T270	3
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T269	1		T270	1		T340	1
all_values[2]	auto[0]	auto[0]	auto[0]	84	1		T268	2		T269	3		T270	2
all_values[2]	auto[0]	auto[1]	auto[0]	81	1		T268	1		T269	2		T270	2
all_values[2]	auto[1]	auto[0]	auto[1]	53	1		T269	1		T270	1		T340	1
all_values[2]	auto[1]	auto[1]	auto[1]	57	1		T268	1		T269	1		T270	2
all_values[3]	auto[0]	auto[0]	auto[0]	95	1		T268	1		T269	2		T270	3
all_values[3]	auto[0]	auto[1]	auto[0]	70	1		T268	3		T269	2		T270	2
all_values[3]	auto[1]	auto[0]	auto[1]	69	1		T269	1		T270	1		T340	1
all_values[3]	auto[1]	auto[1]	auto[1]	41	1		T269	2		T270	1		T341	2
all_values[4]	auto[0]	auto[0]	auto[0]	63	1		T268	3		T270	2		T342	4
all_values[4]	auto[0]	auto[0]	auto[1]	25	1		T269	1		T342	2		T343	2
all_values[4]	auto[0]	auto[1]	auto[0]	50	1		T268	1		T270	1		T340	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T269	1		T270	1		T340	1
all_values[4]	auto[1]	auto[0]	auto[1]	47	1		T269	1		T270	1		T342	1
all_values[4]	auto[1]	auto[1]	auto[1]	61	1		T269	4		T270	2		T340	2
all_values[5]	auto[0]	auto[0]	auto[0]	62	1		T268	2		T269	1		T270	1
all_values[5]	auto[0]	auto[0]	auto[1]	20	1		T269	1		T342	2		T343	2
all_values[5]	auto[0]	auto[1]	auto[0]	58	1		T269	1		T270	2		T340	2
all_values[5]	auto[0]	auto[1]	auto[1]	23	1		T270	1		T340	1		T344	1
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T269	3		T270	2		T342	1
all_values[5]	auto[1]	auto[1]	auto[1]	55	1		T268	2		T269	1		T270	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal