Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24025006	1		T1	281		T2	1152		T3	57
full_word	7854000	1		T1	247		T2	154		T3	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31878696	1		T1	528		T2	1306		T3	61
auto[TlIntgErrCmd]	107	1		T252	2		T253	4		T254	3
auto[TlIntgErrData]	112	1		T252	5		T253	4		T254	5
auto[TlIntgErrBoth]	91	1		T252	3		T253	2		T254	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27341208	1		T1	422		T2	1140		T3	57
auto[1]	4537798	1		T1	106		T2	166		T3	4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23260149	1		T1	262		T2	1134		T3	56
auto[TlIntgErrNone]	partial	auto[1]	764576	1		T1	19		T2	18		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	4080919	1		T1	160		T2	6		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3773052	1		T1	87		T2	148		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T253	2		T347	1		T348	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T252	2		T253	2		T254	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T357	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T254	1		T359	1		T352	2
auto[TlIntgErrData]	partial	auto[0]	55	1		T252	2		T253	1		T254	1
auto[TlIntgErrData]	partial	auto[1]	45	1		T252	2		T253	3		T254	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T360	2		T351	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1		T252	1		T254	1		T353	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T252	1		T253	1		T348	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1		T252	2		T253	1		T254	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T349	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T347	1		T354	2		T357	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19854	1		T115	700		T71	88		T118	465
full_word	3754759	1		T3	10		T13	362		T9	13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3774322	1		T3	10		T13	362		T9	13
auto[TlIntgErrCmd]	112	1		T252	3		T253	6		T254	4
auto[TlIntgErrData]	90	1		T252	5		T253	2		T254	4
auto[TlIntgErrBoth]	89	1		T252	2		T253	2		T254	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3749828	1		T3	10		T13	362		T9	13
auto[1]	24785	1		T115	723		T71	136		T118	726

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1340	1		T115	98		T71	6		T118	4
auto[TlIntgErrNone]	partial	auto[1]	18246	1		T115	602		T71	82		T118	461
auto[TlIntgErrNone]	full_word	auto[0]	3748386	1		T3	10		T13	362		T9	13
auto[TlIntgErrNone]	full_word	auto[1]	6350	1		T115	121		T71	54		T118	265
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T252	2		T253	1		T254	2
auto[TlIntgErrCmd]	partial	auto[1]	74	1		T252	1		T253	4		T254	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T253	1		T356	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T348	1		T359	1		T352	1
auto[TlIntgErrData]	partial	auto[0]	32	1		T252	2		T254	1		T347	1
auto[TlIntgErrData]	partial	auto[1]	49	1		T252	2		T253	2		T254	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T347	1		T354	1		T358	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T252	1		T349	1		T360	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T253	1		T254	1		T347	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T252	2		T253	1		T348	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T353	1		T357	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T254	1		T348	1		T352	1