Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T47 T10 
47         1/1                out_o.err <= '0;
           Tests:       T9 T47 T10 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T12 T9 T22 
50         1/1                out_o.err <= '0;
           Tests:       T12 T9 T22 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T3 T12 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T3 T12 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T3 T12 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T3 T12 
56         1/1                out_o.err <= '0;
           Tests:       T1 T3 T12 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T3 T12 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T3 T12 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T3 T12 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T90,T91

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T12

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T22,T23

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T47,T10
0	0	1	-	-	Covered	T12,T9,T22
0	0	0	1	-	Covered	T1,T3,T12
0	0	0	0	1	Covered	T1,T3,T12
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	5205503	0	0
UpdateCheck_A	2147483647	5205489	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5205503	0	0
T1	9280	74	0	0
T2	14100	0	0	0
T3	4876	5	0	0
T4	11464	0	0	0
T7	5408	0	0	0
T8	34952	0	0	0
T9	2624	15	0	0
T11	8212	0	0	0
T12	10408	10	0	0
T13	274264	521	0	0
T14	0	4	0	0
T15	3376	0	0	0
T17	14632	73	0	0
T20	0	147	0	0
T22	7096	21	0	0
T23	29500	114	0	0
T24	6044	40	0	0
T37	0	148	0	0
T43	0	36	0	0
T55	26616	127	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5205489	0	0
T1	9280	74	0	0
T2	14100	0	0	0
T3	4876	5	0	0
T4	11464	0	0	0
T7	5408	0	0	0
T8	34952	0	0	0
T9	2624	14	0	0
T11	8212	0	0	0
T12	10408	10	0	0
T13	274264	521	0	0
T14	0	4	0	0
T15	3376	0	0	0
T17	14632	73	0	0
T20	0	147	0	0
T22	7096	21	0	0
T23	29500	114	0	0
T24	6044	40	0	0
T37	0	148	0	0
T43	0	36	0	0
T55	26616	127	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T47 T10 
47         1/1                out_o.err <= '0;
           Tests:       T9 T47 T10 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T12 T9 T23 
50         1/1                out_o.err <= '0;
           Tests:       T12 T9 T23 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T3 T12 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T3 T12 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T3 T12 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T3 T12 
56         1/1                out_o.err <= '0;
           Tests:       T1 T3 T12 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T3 T12 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T3 T12 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T3 T12 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T90,T91

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T12

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T23,T59

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T47,T10
0	0	1	-	-	Covered	T12,T9,T23
0	0	0	1	-	Covered	T1,T3,T12
0	0	0	0	1	Covered	T1,T3,T12
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	699155	0	0
UpdateCheck_A	373795953	699154	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	699155	0	0
T1	2320	19	0	0
T2	3525	0	0	0
T3	1219	2	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	2	0	0
T11	2053	0	0	0
T12	2602	3	0	0
T13	34283	69	0	0
T17	1829	19	0	0
T22	0	4	0	0
T23	0	25	0	0
T24	0	9	0	0
T55	0	28	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	699154	0	0
T1	2320	19	0	0
T2	3525	0	0	0
T3	1219	2	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	2	0	0
T11	2053	0	0	0
T12	2602	3	0	0
T13	34283	69	0	0
T17	1829	19	0	0
T22	0	4	0	0
T23	0	25	0	0
T24	0	9	0	0
T55	0	28	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T47 T10 
47         1/1                out_o.err <= '0;
           Tests:       T9 T47 T10 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T12 T9 T23 
50         1/1                out_o.err <= '0;
           Tests:       T12 T9 T23 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T3 T12 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T3 T12 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T3 T12 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T3 T12 
56         1/1                out_o.err <= '0;
           Tests:       T1 T3 T12 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T3 T12 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T3 T12 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T3 T12 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T90,T91

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T12

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T23,T59

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T47,T10
0	0	1	-	-	Covered	T12,T9,T23
0	0	0	1	-	Covered	T1,T3,T12
0	0	0	0	1	Covered	T1,T3,T12
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	698843	0	0
UpdateCheck_A	373795953	698840	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	698843	0	0
T1	2320	19	0	0
T2	3525	0	0	0
T3	1219	1	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	2	0	0
T11	2053	0	0	0
T12	2602	3	0	0
T13	34283	68	0	0
T17	1829	18	0	0
T22	0	4	0	0
T23	0	24	0	0
T24	0	9	0	0
T55	0	26	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	698840	0	0
T1	2320	19	0	0
T2	3525	0	0	0
T3	1219	1	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	2	0	0
T11	2053	0	0	0
T12	2602	3	0	0
T13	34283	68	0	0
T17	1829	18	0	0
T22	0	4	0	0
T23	0	24	0	0
T24	0	9	0	0
T55	0	26	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T47 T10 
47         1/1                out_o.err <= '0;
           Tests:       T9 T47 T10 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T12 T9 T23 
50         1/1                out_o.err <= '0;
           Tests:       T12 T9 T23 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T3 T12 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T3 T12 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T3 T12 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T3 T12 
56         1/1                out_o.err <= '0;
           Tests:       T1 T3 T12 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T3 T12 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T3 T12 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T3 T12 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T90,T91

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T12

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T23,T59

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T47,T10
0	0	1	-	-	Covered	T12,T9,T23
0	0	0	1	-	Covered	T1,T3,T12
0	0	0	0	1	Covered	T1,T3,T12
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	698787	0	0
UpdateCheck_A	373795953	698785	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	698787	0	0
T1	2320	18	0	0
T2	3525	0	0	0
T3	1219	1	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	2	0	0
T11	2053	0	0	0
T12	2602	2	0	0
T13	34283	68	0	0
T17	1829	18	0	0
T22	0	4	0	0
T23	0	24	0	0
T24	0	9	0	0
T55	0	24	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	698785	0	0
T1	2320	18	0	0
T2	3525	0	0	0
T3	1219	1	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	2	0	0
T11	2053	0	0	0
T12	2602	2	0	0
T13	34283	68	0	0
T17	1829	18	0	0
T22	0	4	0	0
T23	0	24	0	0
T24	0	9	0	0
T55	0	24	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T47 T10 
47         1/1                out_o.err <= '0;
           Tests:       T9 T47 T10 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T12 T9 T22 
50         1/1                out_o.err <= '0;
           Tests:       T12 T9 T22 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T3 T12 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T3 T12 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T3 T12 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T3 T12 
56         1/1                out_o.err <= '0;
           Tests:       T1 T3 T12 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T3 T12 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T3 T12 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T3 T12 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T90,T91

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T12

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T22,T23

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T47,T10
0	0	1	-	-	Covered	T12,T9,T22
0	0	0	1	-	Covered	T1,T3,T12
0	0	0	0	1	Covered	T1,T3,T12
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	698233	0	0
UpdateCheck_A	373795953	698231	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	698233	0	0
T1	2320	18	0	0
T2	3525	0	0	0
T3	1219	1	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	2	0	0
T11	2053	0	0	0
T12	2602	2	0	0
T13	34283	68	0	0
T17	1829	18	0	0
T22	0	5	0	0
T23	0	25	0	0
T24	0	8	0	0
T55	0	24	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	698231	0	0
T1	2320	18	0	0
T2	3525	0	0	0
T3	1219	1	0	0
T4	1433	0	0	0
T7	1352	0	0	0
T8	4369	0	0	0
T9	0	1	0	0
T11	2053	0	0	0
T12	2602	2	0	0
T13	34283	68	0	0
T17	1829	18	0	0
T22	0	5	0	0
T23	0	25	0	0
T24	0	8	0	0
T55	0	24	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T10 T90 
47         1/1                out_o.err <= '0;
           Tests:       T9 T10 T90 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T73 T92 
50         1/1                out_o.err <= '0;
           Tests:       T9 T73 T92 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T13 T9 T55 
53         1/1                out_o.part <= part_i;
           Tests:       T13 T9 T55 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T13 T9 T55 
55         1/1                out_o.attr <= Wip;
           Tests:       T13 T9 T55 
56         1/1                out_o.err <= '0;
           Tests:       T13 T9 T55 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T13 T9 T55 
59         1/1                out_o.attr <= Valid;
           Tests:       T13 T9 T55 
60         1/1                out_o.err <= err_i;
           Tests:       T13 T9 T55 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T9,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T90,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T55

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T73,T92,T49

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T10,T90
0	0	1	-	-	Covered	T9,T73,T92
0	0	0	1	-	Covered	T13,T9,T55
0	0	0	0	1	Covered	T13,T9,T55
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	602861	0	0
UpdateCheck_A	373795953	602859	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602861	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	2	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	37	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	2	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	7	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602859	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	2	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	37	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	2	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	7	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T10 T90 
47         1/1                out_o.err <= '0;
           Tests:       T9 T10 T90 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T73 T45 
50         1/1                out_o.err <= '0;
           Tests:       T9 T73 T45 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T13 T9 T55 
53         1/1                out_o.part <= part_i;
           Tests:       T13 T9 T55 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T13 T9 T55 
55         1/1                out_o.attr <= Wip;
           Tests:       T13 T9 T55 
56         1/1                out_o.err <= '0;
           Tests:       T13 T9 T55 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T13 T9 T55 
59         1/1                out_o.attr <= Valid;
           Tests:       T13 T9 T55 
60         1/1                out_o.err <= err_i;
           Tests:       T13 T9 T55 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T9,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T90,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T55

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T73,T45,T92

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T10,T90
0	0	1	-	-	Covered	T9,T73,T45
0	0	0	1	-	Covered	T13,T9,T55
0	0	0	0	1	Covered	T13,T9,T55
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	602524	0	0
UpdateCheck_A	373795953	602521	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602524	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	2	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	37	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	1	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	6	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602521	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	2	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	37	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	1	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	6	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T10 T90 
47         1/1                out_o.err <= '0;
           Tests:       T9 T10 T90 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T73 T92 
50         1/1                out_o.err <= '0;
           Tests:       T9 T73 T92 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T13 T9 T55 
53         1/1                out_o.part <= part_i;
           Tests:       T13 T9 T55 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T13 T9 T55 
55         1/1                out_o.attr <= Wip;
           Tests:       T13 T9 T55 
56         1/1                out_o.err <= '0;
           Tests:       T13 T9 T55 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T13 T9 T55 
59         1/1                out_o.attr <= Valid;
           Tests:       T13 T9 T55 
60         1/1                out_o.err <= err_i;
           Tests:       T13 T9 T55 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T9,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T90,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T55

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T73,T92,T94

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T10,T90
0	0	1	-	-	Covered	T9,T73,T92
0	0	0	1	-	Covered	T13,T9,T55
0	0	0	0	1	Covered	T13,T9,T55
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	602819	0	0
UpdateCheck_A	373795953	602819	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602819	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	2	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	37	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	1	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	6	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602819	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	2	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	37	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	1	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	6	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T9 T10 T90 
47         1/1                out_o.err <= '0;
           Tests:       T9 T10 T90 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T9 T73 T45 
50         1/1                out_o.err <= '0;
           Tests:       T9 T73 T45 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T13 T9 T55 
53         1/1                out_o.part <= part_i;
           Tests:       T13 T9 T55 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T13 T9 T55 
55         1/1                out_o.attr <= Wip;
           Tests:       T13 T9 T55 
56         1/1                out_o.err <= '0;
           Tests:       T13 T9 T55 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T13 T9 T55 
59         1/1                out_o.attr <= Valid;
           Tests:       T13 T9 T55 
60         1/1                out_o.err <= err_i;
           Tests:       T13 T9 T55 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T13,T9,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T90,T91,T93

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T9,T55

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T73,T45,T92

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T9,T55

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T9,T10,T90
0	0	1	-	-	Covered	T9,T73,T45
0	0	0	1	-	Covered	T13,T9,T55
0	0	0	0	1	Covered	T13,T9,T55
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	373795953	602281	0	0
UpdateCheck_A	373795953	602280	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602281	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	1	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	36	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	1	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	6	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373795953	602280	0	0
T4	1433	0	0	0
T8	4369	0	0	0
T9	656	1	0	0
T13	34283	62	0	0
T14	0	1	0	0
T15	844	0	0	0
T17	1829	0	0	0
T20	0	36	0	0
T22	1774	1	0	0
T23	7375	4	0	0
T24	1511	1	0	0
T37	0	37	0	0
T43	0	9	0	0
T55	6654	6	0	0